Lenovo 59P5107 Datenblatt PDF herunterladen (Seite 85)

Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 85

PWRGOOD I

PWRGOOD (Power Good) is an input. The processor requires this signal to be a

clean indication that all processor clocks and power supplies are stable and within

their specifications. “Clean” implies that the signal will remain low (capable of

sinking leakage current), without glitches, from the time that the power supplies are

turned on until they come within specification. The signal must then transition

monotonically to a high state. Figure 12 illustrates the relationship of PWRGOOD to

the RESET# signal. PWRGOOD may be driven inactive at any time, but clocks and

power must again be stable before a subsequent rising edge of PWRGOOD. It must

also meet the minimum pulse width specification in Table 14, and be followed by a 1

mS RESET# pulse.

The PWRGOOD signal must be supplied to the processor; it is used to protect

internal circuits against voltage sequencing issues. It should be driven high

throughout boundary scan operation.

REQ[4:0]# I/O

REQ[4:0]# (Request Command) must connect the appropriate pins of all processor

system bus agents. They are asserted by the current bus owner to define the

currently active transaction type. These signals are source synchronous to

ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking

of these signals.

RESET# I

Asserting the RESET# signal resets all processors to known states and invalidates

their internal caches without writing back any of their contents. For a power-on

Reset, RESET# must stay active for at least one millisecond after V

CC and BCLK

have reached their proper specifications. On observing active RESET#, all system

bus agents will deassert their outputs within two clocks. RESET# must not be kept

asserted for more than 10ms.

A number of bus signals are sampled at the active-to-inactive transition of RESET#

for power-on configuration. These configuration options are described in the Section

7.1.

This signal does not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

RS[2:0]#

RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins of all processor system bus agents.

RSP# I

RSP# (Response Parity) is driven by the response agent (the agent responsible for

completion of the current transaction) during assertion of RS[2:0]#, the signals for

which RSP# provides parity protection. It must connect to the appropriate pins of all

processor system bus agents.

A correct parity signal is high when an even number of covered signals are low and

low when an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is

also high, since this indicates it is not being driven by any agent guaranteeing

correct parity.

SKTOCC# O

SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate

that the processor is present.

SLP# I

SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the

Sleep state. During Sleep state, the processor stops providing internal clock signals

to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in

this state will not recognize snoops or interrupts. The processor will recognize only

assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK

input while in Sleep state. When SLP# is deasserted, the processor exits Sleep

state and returns to Stop-Grant state, restarting its internal clock signals to the bus

and processor core units.

Table 36. Signal Definitions (Sheet 7 of 9)

Name Type Description

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 ... 101 102

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