Lenovo 59P5107 Datenblatt PDF herunterladen (Seite 95)

Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 95

BINIT# may be recognized while the processor is in Stop-Grant state. When STPCLK# is still

asserted at the completion of the BINIT# bus initialization, the processor may remain in Stop-Grant

mode. When STPCLK# is not asserted at the completion of the BINIT# bus initialization, the

processor may return to Normal state.

RESET# may cause the processor to immediately initialize itself, but the processor may stay in

Stop-Grant state. A transition back to the Normal state may occur with the deassertion of the

STPCLK# signal. When re-entering the Stop-Grant state from the sleep state, STPCLK# should

only be deasserted one or more bus clocks after the deassertion of SLP#.

A transition to the HALT/Grant Snoop state may occur when the processor detects a snoop on the

system bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5) may occur with

the assertion of the SLP# signal.

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] may be latched by the

processor, and only serviced when the processor returns to the Normal state. Only one occurrence

of each event may be recognized upon return to the Normal state.

7.2.4 HALT/Grant Snoop State—State 4

The processor may respond to snoop transactions on the system bus while in Stop-Grant state or in

AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant

Snoop state. The processor may stay in this state until the snoop on the system bus has been

serviced (whether by the processor or another agent on the system bus). After the snoop is serviced,

the processor may return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.

7.2.5 Sleep State—State 5

The Sleep state is a very low power state in which each processor maintains its context, maintains

the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state may only be

entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin may be asserted, causing

the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT

states.

Snoop events that occur while in Sleep state or during a transition into or out of Sleep state may

cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching

interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)

are allowed on the system bus while the processor is in Sleep state. Any transition on an input

signal before the processor has returned to Stop-Grant state may result in unpredictable behavior.

When RESET# is driven active while the processor is in the Sleep state, and held active as

specified in the RESET# pin specification, the processor may reset itself, ignoring the transition

through Stop-Grant state. When RESET# is driven active while the processor is in the Sleep state,

the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to

ensure the processor correctly executes the reset sequence.

Once in the Sleep state, the SLP# pin may be deasserted when another asynchronous system bus

event occurs. The SLP# pin should only be asserted when the processor (and all logical processors

within the physical processor) is in the Stop-Grant state. SLP# assertions while the processors are

not in the Stop-Grant state is out of specification and may result in illegal operation.

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