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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 19

2.7 Reserved Or Unused Pins

All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to

, V

, or to any other signal (including one another) may result in component malfunction or

incompatibility with future processors. See Chapter 5.0 for a pin listing of the processor and for the

location of all Reserved pins.

For reliable operation, unused inputs or bidirectional signals should always be connected to an

appropriate signal level. In a system-level design, on-die termination has been included on the

processor to allow signal termination to be accomplished by the processor silicon. Most unused

AGTL+ inputs should be left as no connects, as AGTL+ termination is provided on the processor

silicon. However, see Table 5 for details on AGTL+ signals that do not include on-die termination.

Unused active high inputs should be connected through a resistor to ground (V

). Unused outputs

may be left unconnected, however this may interfere with some TAP functions, complicate debug

probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional

signals to power or ground. When tying any signal to power or ground, a resistor may also allow

for system testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same

value for the on-die termination resistors (R

). See Table 12.

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die

termination. Inputs and all used outputs must be terminated on the baseboard. Unused outputs may

be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated

may interfere with some TAP functions, complicate debug probing, and prevent boundary scan

testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design

Guide.

All TESTHI[6:0] pins should be individually connected to V

through a pull-up resistor which

matches the trace impedance within

±10 Ω. TESTHI[3:0] and TESTHI[6:5] may all be tied

together and pulled up to V

with a single resistor when desired. However, utilization of the

boundary scan test may not be functional when these pins are connected together. TESTHI4 must

always be pulled up independently from the other TESTHI pins. For optimum noise margin, all

pull-up resistor values used for TESTHI[6:0] pins should have a resistance value within 20 percent

of the impedance of the baseboard transmission line traces. For example, when the trace impedance

is 50 W, then a pull-up resistor value between 40 and 60 W should be used. The TESTHI[6:0]

termination recommendations provided in the Low Voltage Intel

Xeon

™

Processor Datasheet are

also suitable for the Intel

Xeon

™

processor. However, Intel recommends new designs or designs

undergoing design updates follow the trace impedance matching termination guidelines outlined in

this section.

2.8 System Bus Signal Groups

In order to simplify the following discussion, the system bus signals have been combined into

groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as

a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as

well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+

output group as well as the AGTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of

timing parameters. One set is for common clock signals whose timings are specified with respect to

rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source

synchronous signals which are relative to their respective strobe lines (data and address) as well as

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