Lenovo 59P5107 Datenblatt Seite 15

  • Herunterladen
  • Zu meinen Handbüchern hinzufügen
  • Drucken
  • Seite
    / 102
  • Inhaltsverzeichnis
  • LESEZEICHEN
  • Bewertet. / 5. Basierend auf Kundenbewertungen
Seitenansicht 14
Low Voltage Intel
®
Xeon
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
Datasheet 15
2.4.1 Bus Clock
The system bus frequency is set to the maximum supported by the individual processor. BSEL[1:0]
are outputs used to select the system bus frequency. Table 3 defines the possible combinations of
the signals and the frequency associated with each combination. The frequency is determined by
the processor(s), chipset, and clock synthesizer. All system bus agents must operate at the same
frequency. Individual processors may only operate at their specified system bus clock frequency.
Baseboards designed for the Intel
®
Xeon
processor employ a 100/133 MHz system bus clock. On
these baseboards, BSEL[1:0] are considered ‘reserved’ at the processor socket.
2.5 PLL Filter
V
CCA
and V
CCIOPLL
are power sources required by the processor PLL clock generator. This
requirement is identical to that of the Intel Xeon
processor. Since these PLLs are analog in nature,
they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades
external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this
degradation, these supplies must be low pass filtered from V
CC
. A typical filter topology is shown
in Figure 1.
The AC low-pass requirements, with input at V
CC
and output measured across the capacitor (C
A
or
C
IO
in Figure 1), is as follows:
< 0.2 dB gain in pass band
< 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)
> 34 dB attenuation from 1 MHz to 66 MHz
> 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter
refer to the appropriate platform design guidelines.
Table 3. System Bus Clock Frequency Select Truth Table for BSEL[1:0]
BSEL1 BSEL0 Bus Clock Frequency
L L 100 MHz
L H 133 MHz
HL Reserved
HH Reserved
Seitenansicht 14
1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 101 102

Kommentare zu diesen Handbüchern

Keine Kommentare