Lenovo 59P5107 Datenblatt PDF herunterladen (Seite 79)

Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 79

5.2 Signal Definitions

Table 36. Signal Definitions (Sheet 1 of 9)

Name Type Description

A[35:3]#

I/O

A[35:3]# (Address) define a 2

byte physical memory address space. In sub-phase

1 of the address phase, these pins transmit the address of a transaction.

In sub-phase 2, these pins transmit transaction type information. These signals

must connect the appropriate pins of all agents on the system bus. A[35:3]# are

protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and

are latched into the receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processors sample a subset of

the A[35:3]# pins to determine their power-on configuration. See Section 7.1.

A20M# I

When A20M# (Address-20 Mask) is asserted, the processor masks physical

address bit 20 (A20#) before looking up a line in any internal cache and before

driving a read/write transaction on the bus. Asserting A20M# emulates the 8086

processor's address wrap-around at the 1 MByte boundary. Assertion of A20M# is

only supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O write bus transaction.

ADS# I/O

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address

on the A[35:3]# pins. All bus agents observe the ADS# activation to begin parity

checking, protocol checking, address decode, internal snoop, or deferred reply ID

match operations associated with the new transaction. This signal must connect the

appropriate pins on all system bus agents.

ADSTB[1:0]# I/O

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling

edge.

AP[1:0]# I/O

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,

A[35:3]#, and the transaction type on the REQ[4:0]# pins. A correct parity signal is

high when an even number of covered signals are low and low when an odd number

of covered signals are low. This allows parity to be high when all the covered signals

are high. AP[1:0]# should connect the appropriate pins of all system bus agents.

The following table defines the coverage model of these signals.

BCLK[1:0] I

The differential pair BCLK (Bus Clock) determines the bus frequency. All processor

system bus agents must receive these signals to drive their outputs and latch their

inputs.

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing the falling edge of BCLK1.

Request Signals Subphase 1 Subphase 2

A[35:24]# AP0# AP1#

A[23:3]# AP1# AP0#

REQ[4:0]# AP1# AP0#

1 2 ... 74 75 76 77 78 79 80 81 82 83 84 ... 101 102

Kommentare zu diesen Handbüchern

Keine Kommentare

Lenovo 59P5107 Datenblatt Seite 79

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Prozessoren Lenovo 59P5107