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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 27

2.12 AGTL+ System Bus Specifications

Routing topologies are dependent on the number of processors supported and the chipset used in

the design. Please refer to the appropriate platform design guidelines. In most cases, termination

resistors are not required as these are integrated into the processor. See Table 5 for details on which

AGTL+ signals do not include on-die termination.The termination resistors are enabled or disabled

through the ODTEN pin. To enable termination, this pin should be pulled up to V

through a

resistor and to disable termination, this pin should be pulled down to V

through a resistor. For

optimum noise margin, all pull-up and pull-down resistor values used for the ODTEN pin should

have a resistance value within 20 percent of the impedance of the baseboard transmission line

traces. For example, when the trace impedance is 50 W, then a value between 40 and 60 W should

be used. The processor's on-die termination must be enabled for the end agent only. Please refer to

Table 12 for termination resistor values. For more details on platform design see the appropriate

platform design guidelines.

Valid high and low levels are determined by the input buffers via comparing with a reference

voltage called GTLREF.

Table 12 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be

generated on the baseboard using high precision voltage divider circuits. It is important that the

baseboard impedance is held to the specified tolerance, and that the intrinsic trace capacitance for

the AGTL+ signal group traces is known and well-controlled. For more details on platform design

see the appropriate platform design guidelines.

NOTES:

1. The tolerances for this specification have been stated generically to enable system designer to calculate the

minimum values across the range of V

2. GTLREF is generated from V

on the baseboard by a voltage divider of 1 percent resistors. Refer to the

appropriate platform design guidelines for implementation details.

3. R

is the on-die termination resistance measured from V

to 1/3 V

at the AGTL+ output driver. Refer to

the Low Voltage Intel

Xeon™ Processor Cache Signal Integrity Models for I/V characteristics.

4. COMP resistors are pull downs to V

provided on the baseboard with 1% tolerance. See the appropriate

platform design guidelines for implementation details.

5. The V

referred to in these specifications refers to instantaneous V

6. The COMP resistance value varies by platform. Refer to the appropriate platform design guideline for the

recommended COMP resistance value.

7. The values for R

and COMP noted as ‘New Designs’ apply to designs that are optimized for the Intel

Xeon™ processor. Refer to the appropriate platform design guideline for the recommended COMP

resistance value.

2.13 System Bus AC Specifications

The processor system bus timings specified in this section are defined at the processor core (pads).

See Section 5.0 for the pin listing and signal definitions.

Table 12 through Table 18 list the AC specifications associated with the processor system bus.

Table 12. AGTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

GTLREF Bus Reference Voltage 0.63 * V

- 2% 0.63 * V

0.63 * V

+ 2% V 1, 2, 5

Termination Resistance 45 50 55 Ω 3, 7

COMP[1:0] COMP Resistance 49.55 50 50.45 Ω 4, 6, 7

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 ... 101 102

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