Lenovo 59P5107 Datenblatt PDF herunterladen (Seite 13)

Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 13

2.0 Electrical Specifications

2.1 System Bus and GTLREF

Most Low Voltage Intel

Xeon

™

processor system bus signals use Assisted Gunning Transceiver

Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins

and reduced ringing through low voltage swings and controlled edge rates. The processor

termination voltage level is V

, the operating voltage of the processor core. The use of a

termination voltage that is determined by the processor core allows better voltage scaling on the

processor system bus. Because of the speed improvements to data and address busses, signal

integrity and platform design methods become more critical than with previous processor families.

The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine

if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See Table 12

for GTLREF specifications). Termination resistors are provided on the processor silicon and are

terminated to its core voltage (V

). The on-die termination resistors are a selectable feature and

may be enabled or disabled through the ODTEN pin. For end bus agents, on-die termination may

be enabled to control reflections on the transmission line. For middle bus agents, on-die

termination must be disabled. Intel chipsets may also provide on-die termination, thus eliminating

the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to Section 2.12 for

details on ODTEN resistor termination requirements.

Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard.

See Table 5 for details regarding these signals.

The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+

signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the

system bus, including trace lengths, is highly recommended when designing a system.

2.2 Power and Ground Pins

For clean on-chip power distribution, the Low Voltage Intel Xeon processor has 190 V

(power)

and 189 V

(ground) inputs. All V

pins must be connected to the system power plane, while all

pins must be connected to the system ground plane. The processor V

pins must be supplied

the voltage determined by the processor VID (Voltage ID) pins.

2.3 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large average current swings between low and full power states. This may cause

voltages on power planes to sag below their minimum values when bulk decoupling is not

adequate. Larger bulk storage (C

BULK

), such as electrolytic capacitors, supply current during longer

lasting changes in current demand by the component, such as coming out of an idle condition.

Similarly, they act as a storage well for current when entering an idle condition from a running

condition. Care must be taken in the baseboard design to ensure that the voltage provided to the

processor remains within the specifications listed in Table 7. Failure to do so may result in timing

violations or reduced lifetime of the component. For further information and guidelines, refer to the

appropriate platform design guidelines.

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 101 102

Kommentare zu diesen Handbüchern

Keine Kommentare

Lenovo 59P5107 Datenblatt Seite 13

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Prozessoren Lenovo 59P5107