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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 39

3.0 System Bus Signal Quality Specifications

This section documents signal quality metrics used to derive topology and routing guidelines

through simulation. All specifications are made at the processor core (pad measurements).

Source synchronous data transfer requires the clean reception of data signals and their associated

strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage

swing may adversely affect system timings. Ringback and signal non-monotinicity cannot be

tolerated since these phenomena may inadvertently advance receiver state machines. Excessive

signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and may

cause device failure when absolute voltage limits are exceeded. Additionally, overshoot and

undershoot may degrade timing due to the build up of inter-symbol interference (ISI) effects. For

these reasons, it is crucial that the designer assure acceptable signal quality across all systematic

variations encountered in volume manufacturing.

Specifications for signal quality are for measurements at the processor core only and are only

observable through simulation. The same is true for all system bus AC timing specifications in

Section 2.13. Therefore, proper simulation of the processor system bus is the only means to verify

proper timing and signal quality metrics.

3.1 System Bus Clock (BCLK) Signal Quality

Specifications and Measurement Guidelines

Table 19 describes the signal quality specifications at the processor pads for the processor system

bus clock (BCLK) signals. Figure 17 describes the signal quality waveform for the system bus

clock at the processor pads.

Table 19. BCLK Signal Quality Specifications

Parameter Min Max Unit Figure Notes

BCLK[1:0] Overshoot N/A 0.30 V 17

BCLK[1:0] Undershoot N/A 0.30 V 17

BCLK[1:0] Ringback Margin 0.20 N/A V 17

BCLK[1:0] Threshold Region N/A 0.10 V 17

†

† The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling)

absolute voltage the BCLK signal may dip back to after passing the V

(rising) or V

(falling) voltage limits.

This specification is an absolute value.

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