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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 83

FERR#/PBE# O

FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and

its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/

PBE# indicates a floating-point error and will be asserted when the processor

detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/

PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included

for compatibility with systems using MS-DOS*-type floating-point error reporting.

When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the

processor has a pending break event waiting for service. The assertion of FERR#/

PBE# indicates that the processor should be returned to the Normal state. For

additional information on the pending break event functionality, including the

identification of support of the feature and enable/disable information, refer to

volume 3 of the Intel Architecture Software Developer's Manual and the Intel

Processor Identification and the CPUID Instruction application note.

This signal does not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

GTLREF

GTLREF determines the signal reference level for AGTL+ input pins. GTLREF

should be set at 0.63 Vcc. GTLREF is used by the AGTL+ receivers to determine

when a signal is a logical 0 or a logical 1.

HIT#

HITM#

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Any system bus agent may assert both HIT# and HITM# together to indicate

that it requires a snoop stall, which may be continued by reasserting HIT# and

HITM# together.

Since multiple agents may deliver snoop results at the same time, HIT# and HITM#

are wire-OR signals which must connect the appropriate pins of all processor

system bus agents. In order to avoid wire-OR glitches associated with simultaneous

edge transitions driven by multiple drivers, HIT# and HITM# are activated on

specific clock edges and sampled on specific clock edges.

IERR# O

IERR# (Internal Error) is asserted by a processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the

processor system bus. This transaction may optionally be converted to an external

error signal (e.g., NMI) by system core logic. The processor will keep IERR#

asserted until the assertion of RESET#, BINIT#, or INIT#.

This signal does not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

IGNNE#

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. When

IGNNE# is deasserted, the processor generates an exception on a noncontrol

floating-point instruction when a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O write bus transaction.

INIT# I

INIT# (Initialization), when asserted, resets integer registers inside all processors

without affecting their internal caches or floating-point registers. Each processor

then begins execution at the power-on Reset vector configured during power-on

configuration. The processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal and must connect the appropriate pins

of all processor system bus agents.

When INIT# is sampled active on the active to inactive transition of RESET#, then

the processor executes its Built-in Self-Test (BIST).

Table 36. Signal Definitions (Sheet 5 of 9)

Name Type Description

1 2 ... 78 79 80 81 82 83 84 85 86 87 88 ... 101 102

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