Low Voltage Intel
®
Xeon
™
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
Datasheet 41
Table 21. Ringback Specifications for TAP Buffers
Signal
Group
Transition
Maximum Ringback
(with Input Diodes
Present)
Threshold Unit Figure Notes
TAP and
PWRGOOD
L
→ HV
T+(max) TO
V
T-(max)
V
T+(max)
V 20 1, 2, 3, 4
TAP and
PWRGOOD
H
→ LV
T-(min) TO
V
T+(min)
V
T-(min)
V 21 1, 2, 3, 4
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Specifications are for the edge rate of 0.3 - 4.0 V/ns.
3. All values specified by design characterization.
4. Please see Section 3.3 for maximum allowable overshoot.
Figure 18. Low-to-High System Bus Receiver Ringback Tolerance
for AGTL+ and Asynchronous GTL+ Buffers
Figure 19. High-to-Low System Bus Receiver Ringback Tolerance
for AGTL+ and Asynchronous GTL+ Buffers
GTLREF
CC
Noise Margin
-10% Vcc
SS
GTLREF
CC
Noise Margi
+10% Vcc
SS
-10% Vcc
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