Lenovo 59P5107 Datenblatt PDF herunterladen (Seite 40)

Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

40 Datasheet

3.2 System Bus Signal Quality Specifications

and Measurement Guidelines

Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are

available in the appropriate platform design guidelines.

Table 20 provides the signal quality specifications for all processor signals for use in simulating

signal quality at the processor pads.

Maximum allowable overshoot and undershoot specifications for a given duration of time are

detailed in Table 22 through Table 25. Figure 18 shows the system bus ringback tolerance for

low-to-high transitions and Figure 19 shows ringback tolerance for high-to-low transitions.

Figure 17. BCLK[1:0] Signal Integrity Waveform

Crossing

Voltage

Threshold

Region

Overshoot

Undershoot

Ringback

Margin

Rising Edge

Ringback

Falling Edge

Ringback,

BCLK0

BCLK1

Crossing

Voltage

Table 20. Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers

Signal Group Transition

Maximum Ringback

(with Input Diodes Present)

Unit Figure Notes

AGTL+, Asynch GTL+ L → H GTLREF + 0.100*GTLREF V 18 1, 2, 3, 4, 5, 6

AGTL+, Asynch GTL+ H

→ L GTLREF - 0.100*GTLREF V 19 1, 2, 3, 4, 5, 6

NOTES:

1. All signal integrity specifications are measured at the processor core (pads).

2. Specifications are for the edge rate of 0.3 - 4.0 V/ns at the receiver.

3. All values specified by design characterization.

4. Please see Section 3.0 for maximum allowable overshoot.

5. Ringback between GTLREF + 100 mV and GTLREF - 100 mV is not supported.

6. Intel recommends simulations not exceed a ringback value of GTLREF

± 200 mV to allow margin for other

sources of system noise.

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 101 102

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