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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

10 Datasheet

compatible with the Pentium Pro processor system bus. The system bus uses Source-Synchronous

Transfer (SST) of address and data to improve performance, and transfers data four times per bus

clock (4X data transfer rate). Along with the 4X data bus, the address bus may deliver addresses

two times per bus clock and is referred to as a ‘double-clocked’ or 2X address bus. In addition, the

Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus

provide a data bus bandwidth of up to 3.2/4.3 Gigabytes per second. Finally, the system bus also

introduces transactions that are used to deliver interrupts. For a list of features for each processor,

see Table 1 below.

Signals on the system bus use Assisted GTL+ (AGTL+) level voltages which are fully described in

the appropriate platform design guide (refer to Section 1.3).

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted

state when driven to a low level. For example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where

the name does not imply an active state but describes part of a binary sequence (such as address or

data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a

hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“System bus” refers to the interface between the processor, system core logic (the chipset

components), and other bus agents. The system bus is a multiprocessing interface to processors,

memory, and I/O. For this document, “system bus” is used as the generic term for the Intel

Xeon

™

processor scalable system bus.

1.1.1 Processor Packaging Terminology

Commonly used terms are explained here for clarification:

• 604-pin socket - The 604-pin socket contains an additional contact to accept the additional

keying pin on the Low Voltage Intel Xeon processor in the FC-µPGA2 packages at pin

location AE30. The 604-pin socket may also accept processors with the INT-mPGA package.

Since the additional contact for pin AE30 is electrically inert, the 604-pin socket may not have

a solder ball at this location. Therefore, the additional keying pin may not require a baseboard

via nor a surface-mount pad. See the 604-Pin Socket Design Guidelines for details regarding

this socket.

• Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal

solution to the processor.

Table 1. Features Comparison for Low Voltage Intel® Xeon™ Processors

Frequency

# of

supported

Systematic

Agent

Advanced

Transfer

Cache

Front Side

Bus

Frequency

Intel Hyper-

Threading

Technology

Package Socket

1.60 GHz 1 - 2 512-KB 400 MHz Yes

FC-µPGA2

(604 pins)

604-pin

2.0 GHz 1 - 2 512-KB 400 MHz Yes

FC-µPGA2

(604 pins)

604-pin

2.4 GHz 1 - 2 512-KB 533 MHz Yes

FC-µPGA2

(604 pins)

604-pin

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 101 102

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