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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

28 Datasheet

All AGTL+ timings are referenced to GTLREF for both 0 and 1 logic levels unless otherwise

specified.

The timings specified in this section should be used in conjunction with the signal integrity models

provided by Intel. These signal integrity models, which include package information, are available

for the Intel

Xeon

™

processor in IBIS format. AGTL+ layout guidelines are also available in the

appropriate platform design guidelines.

Note: Care should be taken to read all notes associated with a particular timing parameter.

Table 13. System Bus Differential Clock Specifications

T# Parameter Min Nom Max Unit Figure Notes

Front Side Bus Clock Frequency (400 MHz) 100.0 MHz 1

Front Side Bus Clock Frequency (533 MHz)130.07 133.33MHz 1

T1: BCLK[1:0] Period (400 MHz)10.0010.20ns62

T1: BCLK[1:0] Period (533 MHz) 7.5 7.65 ns 62

T2: BCLK[1:0] Period Stability N/A 150 ps 3, 4

T3: TPH BCLK[1:0] Pulse High Time (400 MHz)3.9456.12ns 6

T3: TPH BCLK[1:0] Pulse High Time

(533 MHz)

2.955 3.75 4.59 ns 6

T4: TPL BCLK[1:0] Pulse Low Time (400 MHz) 3.94 5 6.12 ns 6

T4: TPL BCLK[1:0] Pulse Low Time (533 MHz) 2.955 3.75 4.59 ns 6

T5: BCLK[1:0] Rise Time 175 700 ps 65

T6: BCLK[1:0] Fall Time 175 700 ps 65

NOTES:

1. The processor core clock frequency is derived from BCLK.

2. The period specified here is the average period. A given period may vary from this specification as

governed by the period stability specification (T2).

3. For the clock jitter specification, refer to the CK00 Clock Synthesizer/Driver Design Guidelines.

4. In this context, period stability is defined as the worst case timing difference between successive crossover

voltages. In other words, the largest absolute difference between adjacent clock periods must be less than

the period stability.

5. Slew rate is measured between the 35% and 65% points of the clock swing (V

and V

)..

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