Lenovo 59P5107 Datenblatt PDF herunterladen (Seite 29)

Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 29

Table 14. System Bus Common Clock AC Specifications

T# Parameter Min Max Unit Figure Notes

1, 2

T10: Common Clock Output Valid Delay 0.12 1.27 ns 83

T11: Common Clock Input Setup Time 0.65 N/A ns 84

T12: Common Clock Input Hold Time 0.40 N/A ns 84

T13: RESET# Pulse Width 1.00 10.00 ms 11 5, 6, 7

NOTES:

1. Not 100% tested. Specified by design characterization.

2. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V

CROSS

) of the

BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at

the processor core.

3. Valid delay timings for these signals are specified into the test circuit described in Figure 4 and with

GTLREF at 0.63

* V

± 2%.

4. Specification is for a minimum swing defined between AGTL+ V

IL_MAX

to V

IH_MIN

. This assumes an edge

rate of 0.3 V/ns to 4.0 V/ns.

5. RESET# may be asserted (active) asynchronously, but must be deasserted synchronously.

6. This should be measured after V

and BCLK[1:0] become stable.

7. Maximum specification applies only while PWRGOOD is asserted.

Table 15. System Bus Source Synchronous AC Specifications (Sheet 1 of 2)

T# Parameter Min Max Unit Figure Notes

T20: Source Sync. Output Valid Delay (first data/

address only)

0.20 1.3 ns 9, 10 1, 2, 3, 4

T21: T

VBD Source Sync. Data Output Valid Before

Data Strobe (400 MHz)

0.85 ns 10 1, 2, 3, 4, 7

T21: T

VBD Source Sync. Data Output Valid Before

Data Strobe (533 MHz)

0.535 ns 10 1, 2, 3, 4, 7

T22: T

VAD Source Sync. Data Output Valid After Data

Strobe (400 MHz)

0.85 ns 10 1, 2, 3, 4, 7

T22: T

VAD Source Sync. Data Output Valid After Data

Strobe (533 MHz)

0.535 ns 10 1, 2, 3, 4, 7

T23: T

VBA Source Sync. Address Output Valid Before

Address Strobe (400 MHz)

1.88 ns 91, 2, 3, 4, 7

T23: T

VBA Source Sync. Address Output Valid Before

Address Strobe (533 MHz)

1.360 ns 91, 2, 3, 4, 7

T24: T

VAA Source Sync. Address Output Valid After

Address Strobe (400 MHz)

1.88 ns 91, 2, 3, 4, 8

T24: T

VAA Source Sync. Address Output Valid After

Address Strobe (533 MHz)

1.360 ns 91, 2, 3, 4, 8

T25: T

SUSS Source Sync. Input Setup Time 0.21 ns 9, 10 1, 2, 3, 5

T26: THSS Source Sync. Input Hold Time 0.21 ns 9, 10 1, 2, 3, 5

T27: T

SUCC Source Sync. Input Setup Time to BCLK 0.65 ns 9, 10 1, 2, 3, 4, 6

T28: TFASS First Address Strobe to Second Address

Strobe

1/2 BCLKs 9

1, 2, 3, 4, 9,

T29: T

FDSS: First Data Strobe to Subsequent Strobes n/4 BCLKs 10

1, 2, 3, 4,

10, 11, 13

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 101 102

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