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Low Voltage Intel
®
Xeon
™
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
20 Datasheet
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and may
become active at any time during the clock cycle. Table 5 identifies which signals are common
clock, source synchronous and asynchronous.
Table 5. System Bus Signal Groups
Signal Group Type Signals
1
AGTL+ Common Clock Input Synchronous to BCLK[1:0]
BPRI#, BR[3:1]#
3, 4
, DEFER#, RESET#
4
,
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#
7
, BNR#
7
, BPM[5:0]#
2
,
BR0#
2
, DBSY#, DP[3:0]#, DRDY#, HIT#
7
,
HITM#
7
, LOCK#, MCERR#
7
AGTL+ Source Synchronous
I/O
Synchronous to assoc.
strobe
AGTL+ Strobes Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous GTL+ Input
4
Asynchronous
A20M#
5
, IGNNE#
5
, INIT#
6
, LINT0/INTR
5
,
LINT1/NMI
5
, SMI#
6
, SLP#, STPCLK#
Asynchronous GTL+ Output
4
Asynchronous FERR#, IERR#, THERMTRIP#
Asynchronous GTL+ Input/
Output
9
Asynchronous PROCHOT#
System Bus Clock Clock BCLK1, BCLK0
TAP Input
2
Synchronous to TCK TCK, TDI, TMS, TRST#
TAP Output
2
Synchronous to TCK TDO
Power/Other Power/Other
BSEL[1:0], COMP[1:0], GTLREF, ODTEN,
Reserved, SKTOCC#, TESTHI[6:0],VID[4:0],
V
CC
, V
CCA
, V
CCIOPLL
, V
SSA
, V
SS
, V
CCSENSE
,
V
SSSENSE,
PWRGOOD, THERMDA,
THERMDC. VID_V
CC
8
NOTES:
1. Refer to Section 5.2 for signal descriptions.
2. These AGTL+ signal groups are not terminated by the processor. Refer the ITP700 Debug Port Design
Guide and corresponding Design Guide for termination requirements and further details.
3. The Low Voltage Intel
®
Xeon™ processor utilizes only BR0# and BR1#. BR2# and BR3# are not driven by
the processor but must be terminated to V
CC
. For additional details regarding the BR[3:0]# signals, see
Section 5.2 and Section 7.1 and the appropriate Platform Design Guidelines.
4. These signal groups are not terminated by the processor. Refer to the appropriate platform design
guidelines and the ITP700 Debug Port Design Guide for termination recommendations.
5. The volume on these pins during active-to-inactive edge of RESET# determines the multiplier that the
Phase Lock Loop (PLL) will use for internal core clock
6. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration
options. See Section 7.1 for details.
7. These signals may be driven simultaneously by multiple agents (wired-OR).
8. VID_V
CC
is required for correct operation of the Low Voltage Intel
®
Xeon™ Processor. Refer to Figure 16
for details.
9. It is an output only on the 1.60 GHz Low Voltage Intel
®
Xeon™ processor with CPUID of 0F27h.
Signals Associated Strobe
REQ[4:0]#,A[16:3]#
6
ADSTB0#
A[35:17]#
5
ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#
- Low Voltage Intel 1
- Processor at 1
- 1.60 GHz, 2.0 GHz and 2.4 GHz 1
- 2 Datasheet 2
- Contents 3
- Revision History 7
- 8 Datasheet 8
- 1.0 Introduction 9
- 1.1 Terminology 10
- 1.2 State of Data 11
- 1.3 References 11
- 12 Datasheet 12
- 2.0 Electrical Specifications 13
- Decoupling 14
- 2.5 PLL Filter 15
- Figure 1. Typical V 16
- Power Distribution 16
- 2.6 Voltage Identification 17
- 18 Datasheet 18
- 2.7 Reserved Or Unused Pins 19
- 2.8 System Bus Signal Groups 19
- 20 Datasheet 20
- 2.9 Asynchronous GTL+ Signals 21
- 2.10 Maximum Ratings 21
- 22 Datasheet 22
- Datasheet 23 23
- Figure 3. Low Voltage Intel 24
- Processor Voltage and 24
- Datasheet 25 25
- 26 Datasheet 26
- Datasheet 27 27
- 28 Datasheet 28
- Datasheet 29 29
- 30 Datasheet 30
- Datasheet 31 31
- 32 Datasheet 32
- Datasheet 33 33
- 34 Datasheet 34
- Datasheet 35 35
- 36 Datasheet 36
- Figure 15. THERMTRIP# to V 37
- Power Down 38
- Power Up 38
- Datasheet 39 39
- 40 Datasheet 40
- Noise Margi 41
- 42 Datasheet 42
- Datasheet 43 43
- 3.3.4 Activity Factor 44
- Specifications 45
- 46 Datasheet 46
- Datasheet 47 47
- 48 Datasheet 48
- Undershoot Tolerance 49
- 50 Datasheet 50
- 4.0 Mechanical Specifications 51
- 4.1 Mechanical Specifications 52
- Figure 25. Low Voltage Intel 53
- 54 Datasheet 54
- Datasheet 55 55
- 56 Datasheet 56
- 4.3 Insertion Specifications 57
- 4.4 Mass Specifications 57
- 4.5 Materials 57
- 4.6 Markings 58
- 4.7 Processor Pin-Out Diagram 58
- Datasheet 59 59
- 60 Datasheet 60
- 5.1 Processor Pin Assignments 61
- 62 Datasheet 62
- Datasheet 63 63
- 64 Datasheet 64
- Datasheet 65 65
- 66 Datasheet 66
- Datasheet 67 67
- 68 Datasheet 68
- Datasheet 69 69
- 70 Datasheet 70
- Datasheet 71 71
- 72 Datasheet 72
- Datasheet 73 73
- 74 Datasheet 74
- Datasheet 75 75
- 76 Datasheet 76
- Datasheet 77 77
- 78 Datasheet 78
- 5.2 Signal Definitions 79
- 80 Datasheet 80
- 82 Datasheet 82
- Datasheet 83 83
- 84 Datasheet 84
- Datasheet 85 85
- 86 Datasheet 86
- Datasheet 87 87
- 88 Datasheet 88
- 6.0 Thermal Specifications 89
- 90 Datasheet 90
- Datasheet 91 91
- 92 Datasheet 92
- 7.0 Features 93
- 94 Datasheet 94
- 7.2.5 Sleep State—State 5 95
- 7.3 Thermal Monitor 96
- 7.4 Thermal Diode 97
- 98 Datasheet 98
- Debug Port Design Guide 99
- 100 Datasheet 100
- 9.0 Appendix A 101
- 102 Datasheet 102
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