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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 9

1.0 Introduction

The Low Voltage Intel

Xeon

™

processor is based on the Intel

NetBurst

™

micro-architecture,

which operates at significantly higher clock speeds and delivers performance levels that are

significantly higher than previous generations of IA-32 processors. While based on the Intel

NetBurst micro-architecture, it maintains the tradition of compatibility with IA-32 software.

The Intel

NetBurst micro-architecture features begin with innovative techniques that enhance

processor execution such as Hyper Pipelined Technology, a Rapid Execution Engine, Advanced

Dynamic Execution, enhanced Floating Point and Multimedia unit, and Streaming SIMD

Extensions 2 (SSE2). The Hyper Pipelined Technology doubles the pipeline depth in the processor,

allowing the processor to reach much higher core frequencies. The Rapid Execution Engine allows

the two integer ALUs in the processor to run at twice the core frequency, which allows many

integer instructions to execute in one half of the internal core clock period. The Advanced Dynamic

Execution improves speculative execution and branch prediction internal to the processor. The

floating point and multi-media units have been improved by making the registers 128 bits wide and

adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for

double-precision floating point, SIMD integer, and memory management for improvements in

video/multimedia processing, secure transactions, and visual internet applications.

Also part of the Intel NetBurst micro-architecture, the system bus and caches on the Low Voltage

Intel Xeon processor provide tremendous throughput for embedded applications. The 400/533

MHz system bus provides a high-bandwidth pipeline to the system memory and I/O. It is a quad-

pumped bus running off a 100/133

MHz system bus clock making 3.2/4.3 Gigabytes per second

(3,200/4,300 Megabytes per second) data transfer rates possible. The Execution Trace Cache is a

level 1 cache that stores approximately twelve thousand decoded micro-operations, which removes

the decoder latency from the main execution path and increases performance. The Advanced

Transfer Cache is a 512

KB on-die level 2 cache running at the speed of the processor core

providing increased bandwidth over previous micro-architectures.

In addition to the Intel NetBurst micro-architecture, the Low Voltage Intel Xeon processor includes

a ground breaking new technology called Hyper-Threading technology, which enables

multi-threaded software to execute tasks in parallel within the processor resulting in a more

efficient, simultaneous use of processor resources. Embedded applications may realize increased

performance from Hyper-Threading technology today through software and processor evolution.

The combination of Intel NetBurst micro-architecture and Hyper-Threading technology delivers

outstanding performance, throughput, and headroom for peak software workloads resulting in

faster response times and improved scalability.

The Low Voltage Intel Xeon processor is intended for high performance embedded systems with

up to two processors on a single bus. The processor supports both uni- and dual-processor designs

and includes manageability features.

The Low Voltage Intel Xeon processor is packaged in a 604-pin Flip Chip Micro-Pin Grid Array

(FC-µPGA2) package, and utilizes a surface mount ZIF socket with 604 pins. Mechanical

components used for attaching thermal solutions to the baseboard should have a high degree of

commonality with the thermal solution components enabled for the Low Voltage Intel Xeon

processor. Heatsinks and retention mechanisms have been designed with manufacturability as a

high priority. Hence, mechanical assembly may be completed from the top of the baseboard.

The Low Voltage Intel Xeon processor uses a scalable system bus protocol referred to as the

“system bus” in this document. The processor system bus utilizes a split-transaction, deferred reply

protocol similar to that introduced by the Intel

Pentium

Pro processor system bus, but is not

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