Lenovo 59P5107 Datenblatt PDF herunterladen (Seite 30)

Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

30 Datasheet

T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay

(400 MHz)

8.80 10.20 ns 10 1, 2, 3, 4, 12

T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay

(533 MHz)

6.47 8.00 ns 10 1, 2, 3, 4, 12

T31: Address Strobe Output Valid Delay (400 MHz) 2.27 4.23 ns 91, 2, 3

T31: Address Strobe Output Valid Delay (533 MHz) 1.655 3.50 ns 91, 2, 3

NOTES:

1. Not 100% tested. Specified by design characterization.

2. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source

synchronous data signals are referenced to the falling edge of their associated data strobe. Source

synchronous address signals are referenced to the rising and falling edge of their associated address

strobe. All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core.

3. Unless otherwise noted, these specifications apply to both data and address timings.

4. Valid delay timings for these signals are specified into the test circuit described in Figure 4 and with

GTLREF at 0.63 *

± 2%.

5. Specification is for a minimum swing defined between AGTL+ V

IL_MAX

to V

IH_MIN

. This assumes an edge

rate of 0.3 V/ns to 4.0 V/ns.

6. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to

each respective strobe.

7. This specification represents the minimum time the data or address may be valid before its strobe. Refer to

the appropriate platform design guidelines for more information on the definitions and use of these

specifications.

8. This specification represents the minimum time the data or address may be valid after its strobe. Refer to

the appropriate platform design guidelines for more information on the definitions and use of these

specifications.

9. The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of

ADSTB#.

10.For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.

11.The second data strobe (the falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns)

after the first falling edge of DSTBp#. The third data strobe (the falling edge of DSTBp#) must come

approximately 2/4 BCLK period (5 ns) after the first falling edge of DSTBp#. The last data strobe (the falling

edge of DSTBn#) must come approximately 3/4 BCLK period (7.5 ns) after the first falling edge of DSTBp#.

12.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.

13.This specification reflects a typical value, not a minimum or maximum.

Table 16. Miscellaneous Signals+ AC Specifications

T# Parameter Min Max Unit Figure Notes

T35: Async GTL+ input pulse width 2 N/A BCLKs 1, 2, 3

T36: PWRGOOD to RESET# de-assertion time 1 10 ms 12 1, 2, 3

T37: PWRGOOD inactive pulse width 10 N/A BCLKs 12 1, 2, 3, 4

T38: PROCHOT# pulse width 500 µs 14 1, 2, 3, 4, 5

T39: THERMTRIP# to Vcc Removal 0.5 s 15

NOTES:

1. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing

Voltage (V

CROSS

). All Asynchronous GTL+ signal timings are referenced at GTLREF.

2. These signals may be driven asynchronously.

3. Refer to Section 7.2 for additional timing requirements for entering and leaving low power states.

4. Refer to the PWRGOOD signal definition in Section 5.2 for more detail information on behavior of the

signal.

5. Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the

assertion and before the deassertion of PROCHOT# for the processor to enable or disable the TCC. This

specification applies to PROCHOT# when asserted by the processor. A minimum pulse width of 500 µs is

recommended when PROCHOT# is asserted by the system.

Table 15. System Bus Source Synchronous AC Specifications (Sheet 2 of 2)

T# Parameter Min Max Unit Figure Notes

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 101 102

Kommentare zu diesen Handbüchern

Keine Kommentare

Lenovo 59P5107 Datenblatt Seite 30

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Prozessoren Lenovo 59P5107