Lenovo 59P5107 Datenblatt Seite 101

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Low Voltage Intel
®
Xeon
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
Datasheet 101
9.0 Appendix A
9.1 Processor Core Frequency Determination
To allow system debug and multiprocessor configuration flexibility, the core frequency of the
processor may be configured using an MSR.
Clock multiplying within the processor is provided by the internal Phase Lock Loop (PLL), which
requires a constant frequency BCLK inputs. For Spread Spectrum Clocking, please refer to the
CK00 Clock Synthesizer/Driver Design Guidelines and the CK408 Clock Synthesizer/Driver
Design Guidelines
. The system bus frequency ratio cannot be changed dynamically during normal
processor operation, nor can it be changed during any low power modes. The system bus frequency
ratio can be changed when RESET# is active, assuming that all Reset specifications are met.
However, the reprogrammed values will not take effect until after the processor has undergone a
warm RESET.
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