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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 93

7.0 Features

7.1 Power-On Configuration Options

The Low Voltage Intel

Xeon

™

processor has several configuration options that are determined by

the state of specific processor pins at the active-to-inactive transition of the processor RESET#

signal. These configuration options cannot be changed except by another reset. Both power on and

software induced resets reconfigure the processor(s).

7.2 Clock Control and Low Power States

The processor allows the use of AutoHALT, Stop-Grant and Sleep states to reduce power

consumption by stopping the clock to internal sections of the processor, depending on each

particular state. See Figure 36 for a visual representation of the processor low power states.

Due to the inability of processors to recognize bus transactions during the Sleep state,

multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the

other processor in the Normal or Stop-Grant state.

7.2.1 Normal State—State 1

This is the normal operating state for the processor.

7.2.2 AutoHALT Powerdown State—State 2

AutoHALT is a low power state entered when the processor executes the HALT instruction. The

processor may transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#,

LINT[1:0] (NMI, INTR), or an interrupt delivered over the system bus. RESET# may cause the

processor to immediately initialize itself.

Table 38. Power-On Configuration Option Pins

Configuration Option Pin

Notes

Output tri state SMI#

Execute BIST (Built-In Self Test) INIT#

In Order Queue de-pipelining (set IOQ depth to 1) A7#

Disable MCERR# observation A9#

Disable BINIT# observation A10#

APIC cluster ID (0-3) A[12:11]# 2

Disable bus parking A15#

Disable Hyper-Threading Technology A31#

Symmetric agent arbitration ID BR[3:0]# 3

NOTES:

1. Asserting this signal during active-to-inactive edge of RESET# may select the corresponding option.

2. The Low Voltage Intel Xeon processor does not support this feature, therefore platforms utilizing this

processor should not use these configuration pins.

3. The Low Voltage Intel Xeon processor utilizes only BR0# and BR1# signals. Two-way platforms must not

utilize BR2# and BR3# signals.

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