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Low Voltage Intel
®
Xeon
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
26 Datasheet
Table 10. TAP and PWRGOOD Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes
1
V
HYS
TAP Input Hysteresis 200 300 7
V
T+
TAP input low to high
threshold voltage
0.5 * (V
CC
+ V
HYS_MIN
) 0.5 * (V
CC
+ V
HYS_MAX
) 4
V
T-
TAP input high to low
threshold voltage
0.5 * (V
CC
- V
HYS_MAX
) 0.5 * (V
CC
- V
HYS_MIN
) 4
V
OH
Output High Voltage N/A V
CC
V 2, 4
I
OL
Output Low Current 40 mA 5, 6
I
HI
Pin Leakage High N/A 100 µA 9
I
LO
Pin Leakage Low N/A 500 µA 8
R
ON
Buffer On Resistance 8.75 13.75 3
NOTES:.
1. All outputs are open drain.
2. TAP signal group must meet the system signal quality specification in Chapter 3.0.
3. Refer to the Low Voltage Intel
®
Xeon™ Processor Signal Integrity Models for I/V characteristics.
4. The V
CC
referred to in these specifications refers to instantaneous V
CC
.
5. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
6. V
OL_MAX
of 0.300V is ensured when driving a test load.
7. V
HYS
represents the amount of hysteresis, nominally centered about 0.5*V
CC
, for all TAP inputs.
8. Leakage to V
CC
with Pin held at 300 mV.
9. Leakage to V
SS
with pin held at V
CC
.
Table 11. Asynchronous GTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes
7
V
IH
Input High Voltage 1.10 * GTLREF V
CC
V 2, 4, 6
V
IL
Input Low Voltage 0.0 0.90 * GTLREF V 3, 5
V
OH
Output High Voltage N/A VCC V 1, 4, 6
I
OL
Output Low Current 50 mA 7, 8
I
HI
Pin Leakage High N/A 100 µA 10
I
LO
Pin Leakage Low N/A 500 µA 9
R
ON
Buffer On Resistance 7 11 5
NOTES:
1. All outputs are open drain.
2. V
IH
is defined as the minimum voltage level at a receiving agent that may be interpreted as a logical high
value.
3. V
IL
is defined as the maximum voltage level at a receiving agent that may be interpreted as a logical low
value.
4. V
IH
and V
OH
may experience excursions above V
CC
. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.0.
5. Refer to the Low Voltage Intel
®
Xeon™ Processor Signal Integrity Models for I/V characteristics.
6. The V
CC
referred to in these specifications refers to instantaneous V
CC
.
7. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
8. V
OL_MAX
of 0.450 V is ensured when driving into a test load as indicated in Figure 4, with R
TT
enabled.
9. Leakage to V
CC
with Pin held at 300 mV.
10.Leakage to V
SS
with pin held at V
CC
.
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