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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

86 Datasheet

SMI# I

SMI# (System Management Interrupt) is asserted asynchronously by system logic.

On accepting a System Management Interrupt, processors save the current state

and enter System Management Mode (SMM). An SMI Acknowledge transaction is

issued, and the processor begins program execution from the SMM handler.

When SMI# is asserted during the deassertion of RESET# the processor will

tri-state its outputs.

STPCLK# I

STPCLK# (Stop Clock), when asserted, causes processors to enter a low power

Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and

stops providing internal clock signals to all processor core units except the system

bus and APIC units. The processor continues to snoop bus transactions and service

interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor

restarts its internal clock to all units and resumes execution. The assertion of

STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK I

TCK (Test Clock) provides the clock input for the processor Test Bus (also known as

the Test Access Port).

TDI I

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO O

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides

the serial output needed for JTAG specification support.

TESTHI[6:0] I

All TESTHI[6:0] pins should be individually connected to V

via a pull-up resistor

which matches the trace impedance within a range of ±10 ohms. TESTHI[3:0] and

TESTHI[6:5] may all be tied together and pulled up to V

with a single resistor

when desired. However, utilization of boundary scan test will not be functional when

these pins are connected together. TESTHI4 must always be pulled up

independently from the other TESTHI pins. For optimum noise margin, all pull-up

resistor values used for TESTHI[6:0] pins should have a resistance value within ±20

percent of the impedance of the baseboard transmission line traces. For example,

when the trace impedance is 50

Ω, then a value between 40 Ω and 60 Ω should be

used. The TESTHI[6:0] termination recommendations provided in the Intel

Xeon

processor datasheet are still suitable for the Intel® Xeon

processor with 512 KB

L2 cache. However, Intel recommends new designs or designs undergoing design

updates follow the trace impedance matching termination guidelines given in this

section.

THERMDA O Thermal Diode Anode

THERMDC O Thermal Diode Cathode

THERMTRIP# O

Activation of THERMTRIP# (Thermal Trip) indicates the processor junction

temperature has reached a level beyond which permanent silicon damage may

occur. Measurement of the temperature is accomplished through an internal thermal

sensor which is configured to trip at approximately 135 °C. To properly protect the

processor, power must be removed upon THERMTRIP# becoming active. See

Figure 15, “THERMTRIP# to VCC Timing” on page 37 for the appropriate power

down sequence and timing requirement. In parallel, the processor will attempt to

reduce its temperature by shutting off internal clocks and stopping all program

execution. Once activated, THERMTRIP# remains latched and the processor will be

stopped until RESET# is asserted. A RESET# pulse will reset the processor and

execution will begin at the boot vector. When the temperature has not dropped

below the trip level, the processor will assert THERMTRIP# and return to the

shutdown state. The processor releases THERMTRIP# when RESET# is activated

even when the processor is still too hot.

This signal do not have on-die termination and must be terminated at the end

agent. See the appropriate platform design guidelines for additional

information.

Table 36. Signal Definitions (Sheet 8 of 9)

Name Type Description

1 2 ... 81 82 83 84 85 86 87 88 89 90 91 ... 101 102

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