Lenovo 59P5107 Datenblatt Seite 84

  • Herunterladen
  • Zu meinen Handbüchern hinzufügen
  • Drucken
  • Seite
    / 102
  • Inhaltsverzeichnis
  • LESEZEICHEN
  • Bewertet. / 5. Basierend auf Kundenbewertungen
Seitenansicht 83
Low Voltage Intel
®
Xeon
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
84 Datasheet
LINT[1:0] I
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all system bus
agents. When the APIC functionality is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# I/O
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of all processor system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
MCERR# I/O
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
Enabled or disabled.
Asserted, when configured, for internal errors along with IERR#.
Asserted, when configured, by the request initiator of a bus transaction after it
observes an error.
Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the
IA-32 Software
Developer’s Manual, Volume 3: System Programming Guide
.
Since multiple agents may drive this signal at the same time, MCERR# is a wire-OR
signal which must connect the appropriate pins of all processor system bus agents.
In order to avoid wire-OR glitches associated with simultaneous edge transitions
driven by multiple drivers, MCERR# is activated on specific clock edges and
sampled on specific clock edges.
Mechanical
Key
Inert The mechanical key is to prevent compatibility with 603-pin socket.
ODTEN I
ODTEN (On-die termination enable) should be connected to V
CC
to enable on-die
termination for end bus agents. For middle bus agents, pull this signal down via a
resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die
termination will be active, regardless of other states of the bus.
PROCHOT# I/O
PROCHOT# As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain
active until the system deasserts PROCHOT#. See Section 7.3 for more details.
The PROCHOT# is an output only on 1.6 GHz Low Voltage Intel
®
Xeon™ processor
with CPUID of 0F27h.
Table 36. Signal Definitions (Sheet 6 of 9)
Name Type Description
Seitenansicht 83
1 2 ... 79 80 81 82 83 84 85 86 87 88 89 ... 101 102

Kommentare zu diesen Handbüchern

Keine Kommentare