Low Voltage Intel
®
Xeon
™
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
32 Datasheet
falling edge of their associated data strobe. Source synchronous address signals are referenced
to the rising and falling edge of their associated address strobe. All source synchronous
AGTL+ signal timings are referenced at GTLREF at the processor core (pads).
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V
CROSS
. All
AGTL+ strobe signal timings are referenced at GTLREF at the processor core (pads).
4. All AC Timing for he TAP signals are referenced to the TCK signal at 0.5 * V
CC
at the
processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at the 0.5 * V
CC
at the
processor core (pads).
Figure 4. Electrical Test Circuit
Figure 5. TCK Clock Waveform
Vtt Vtt
Rload = 50 ohms
C = 1.2pF
L = 2.4nH
AC Timings
specified at pad.
Zo = 50 ohms, d=420mils, So=169ps/in
*V2
*V3
*V1
t
r
t
p
t
f
CLK
T
r
= T56, T58 (Rise Time)
T
f
= T57, T59 (Fall Time)
T
p
= T55 (Period)
V3: TCK is referenced to 0.5* Vcc.
V1, V2: For rise and fall times, TCK is measured between 20%to 80%points on the waveform.
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