Lenovo AD80582QH056003 Datenblatt PDF herunterladen (Seite 39)

Intel® Xeon® Processor 7400 Series Datasheet 39

Electrical Specifications

13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.

14. This specification reflects a typical value, not a minimum or maximum.

15. For this timing parameter, n = 0 to 1.

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing

Voltage (V

CROSS

). PWRGOOD is referenced to BCLK0 rising edge at 0.5 * V

3. These signals may be driven asynchronously.

4. Refer to Section 7.2 for additional timing requirements for entering and leaving low power states.

5. A minimum pulse width of 500 µs is recommended when FORCEPR# is asserted by the system.

6. Refer to the PWRGOOD signal definition in Section 5 for more details information on behavior of the signal.

7. Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion

and before the deassertion of PROCHOT# for the processor to enable or disable the TCC.

8. Intel recommends the V

power supply also be removed upon assertion of THERMTRIP#.

9. This specification requires that the VID and BSEL signals be sampled no earlier than 10 μs after V

(at

CC_BOOT

voltage) and V

are stable.

10. Parameter must be measured after applicable voltage level is stable. “Stable” means that the power supply

is in regulation as defined by the minimum and maximum DC/AC specifications for all components being

11. The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor.

Measured between (0.3* V

) and (0.7*V

12. See Table 2-19 for BCLK specifications.

Notes:

1. Before the clock that de-asserts RESET#.

2. After the clock that de-asserts RESET#.

Table 2-22. Miscellaneous GTL+ AC Specifications

T# Parameter Min Max Unit Figure

Notes

1, 2, 3, 4

T35: Asynchronous GTL+ input pulse width 8 BCLKs 5

T36: PWRGOOD assertion to RESET# de-assertion 1 10 ms 2-20

T37: BCLK stable to PWRGOOD assertion 10 BCLKs 2-20 6,12

T38: PROCHOT# pulse width 500 µs 2-16 7

T39: THERMTRIP# assertion until V

removed 500 ms 2-17 8

T40: FERR# valid delay from STPCLK# deassertion 0 5 BCLKs 2-21

T41: V

stable to PWRGOOD assertion 0.05 500 ms 2-20 10

T42: PWRGOOD rise time 20 ns 11

T43: V

CC_BOOT

stable to VID / BSEL valid 10 µs 2-20 9,10

T44: VID / BSEL valid to V

stable 100 µs 2-20 10

T48: V

stable to VID / BSEL valid 10 µs 2-20 10

T49: V

CCPLL

stable to PWRGOOD assertion 1 ms 2-20 10

Table 2-23. Front Side Bus AC Specifications (Reset Conditions)

T# Parameter Min Max Unit Figure Notes

T45: Reset Configuration Signals

(A[39:3]#, BR[1:0]#, INIT#, SMI#) Setup Time

480 µs 2-20 1

T46: Reset Configuration Signals

(A[39:3]#, INIT#, SMI#) Hold Time

220BCLKs2-20 2

T47: Reset Configuration Signals

BR[1:0]# Hold Time

22BCLKs2-20 2

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 135 136

Kommentare zu diesen Handbüchern

Keine Kommentare

Lenovo AD80582QH056003 Datenblatt Seite 39

Kommentare zu diesen Handbüchern