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Features

106 Intel® Xeon® Processor 7400 Series Datasheet

7.2.1 Normal State

This is the normal operating state for the processor.

7.2.2 HALT or Extended HALT State

The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state

must be enabled for the processor to remain within its specifications. The

Extended HALT state requires support for dynamic VID transitions in the platform.

7.2.2.1 HALT State

HALT is a low power state entered when the processor has executed the HALT or

MWAIT instruction. When one of the processor cores executes the HALT or MWAIT

instruction, that processor core is halted; however, the other processor cores continue

normal operation. The processor will transition to the Normal state upon the occurrence

of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the

front side bus. RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either

Normal Mode or the HALT state. See the Intel

64 and IA-32 Architectures Software

Developer's Manual, Volume III: System Programming Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT state. When the

system deasserts STPCLK#, the processor will return execution to the HALT state.

While in HALT state, the processor will process front side bus snoops and interrupts.

7.2.2.2 Extended HALT State

Extended HALT state is a low power state entered when all processor cores have

executed the HALT or MWAIT instructions and Extended HALT state has been enabled

via the BIOS. When one of the processor cores executes the HALT instruction, that

processor core is halted; however, the other processor cores continue normal

operation. The Extended HALT state is a lower power state than the HALT state or Stop

Grant state. The Extended HALT state must be enabled for the processor to remain

within its specifications.

The processor will automatically transition to a lower core frequency and voltage

operating point before entering the Extended HALT state. Note that the processor FSB

frequency is not altered; only the internal core frequency is changed. When entering

the low power state, the processor will first switch to the lower bus to core frequency

ratio and then transition to the lower voltage (VID).

While in the Extended HALT state, the processor will process bus snoops.

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Lenovo AD80582QH056003 Datenblatt Seite 106