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Electrical Specifications

38 Intel® Xeon® Processor 7400 Series Datasheet

4. Valid delay timings for these signals are specified into the test circuit described in Figure 2-7 and with

GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * V

5. Specification is for a minimum swing is specified into the test circuit described in Figure 2-7 and defined

between AGTL+ V

IL_MAX

to V

IH_MIN

. This assumes an edge rate of 2.0 V/ns to 3.0 V/ns.

6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.

7. This should be measured after V

and BCLK[1:0] become stable.

8. Maximum specification applies only while PWRGOOD is asserted.

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Not 100% tested. Specified by design characterization.

3. All source synchronous AC timings are referenced to their associated strobe at nominal GTLREF_DATA_MID,

GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. Source synchronous data signals are

referenced to the falling edge of their associated data strobe. Source synchronous address signals are

referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+

signal timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and

GTLREF_ADD_END at the processor pads.

4. Unless otherwise noted, these specifications apply to both data and address timings.

5. Valid delay timings for these signals are specified into the test circuit described in Figure 2-7 and with

GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * V

6. Specification is for a minimum swing into the test circuit described in Figure 2-7 and defined between

AGTL+ V

IL_MAX

to V

IH_MIN

. This assumes an edge rate of 3.0 V/ns to 5.5 V/ns.

7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to

each respective strobe.

8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to

the appropriate platform design guidelines for more information on the definitions and use of these

specifications.

9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to

the appropriate platform design guidelines for more information on the definitions and use of these

specifications.

10. The rising edge of ADSTB# must come approximately 1/2 BCLK period after the falling edge of ADSTB#.

11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.

12. The address strobe setup time is measured with respect to T2. Calculation of the setup time is as follows:

a. If T27 > BCLK period, then the setup time calculated is positive. The value calculated indicates

setup time before T1.

b. If T27 < BCLK period, then the setup time calculated is positive. The value calculated indicates

setup time after T1.

Table 2-21. FSB Source Synchronous AC Specifications

T# Parameter Min Max Unit Figure Notes

1, 2, 3, 4

T20: Source Sync. Output Valid Delay

(first data/address only)

0.00 1.10 ns 2-13,

2-14

T21: T

VBD

Source Sync. Data Output Valid

Before Data Strobe

0.27 ns 2-14 5,8

T22: T

VAD

Source Sync. Data Output Valid

After Data Strobe

0.27 ns 2-14 5,9

T23: T

VBA

Source Sync. Address Output

Valid Before Address Strobe

0.66 ns 2-13 5,8

T24: T

VAA

Source Sync. Address Output

Valid After Address Strobe

0.66 ns 2-13 5,9

T25: T

SUSS

Data Input Setup Time 0.19 ns 2-13,

2-14

T25: T

SUSS

Address Input Setup Time 0.3 ns 2-13,

2-14

T26: T

HSS

Data Input Hold Time 0.19 ns 2-13,

2-14

T26: T

HSS

Address Input Hold Time 0.300 ns 2-13,

2-14

T27: Source Synchronous Address Strobe

Setup Time to BCLK[1:0]

3.5 - (1.875 * n) ns 2-13,

2-14

12, 14, 15,10

T28: Source Synchronous Data Strobe

Setup Time to BCLK[1:0]

4.15 - (0.9375 * n) ns 2-14 11, 14

T30: Data Strobe ‘n’ (DSTBN#) Output

Valid Delay

3.28 4.38 ns 2-14 13

T31: Address Strobe Output Valid Delay 2.81 3.91 ns 2-13

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 135 136

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