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Electrical Specifications
34 Intel® Xeon® Processor 7400 Series Datasheet
2.11.4 Platform Environmental Control Interface (PECI) DC
Specifications
PECI is an Intel proprietary one-wire bus interface that provides a communication
channel between Intel processor and external thermal monitoring devices. The Intel®
Xeon® Processor 7400 Series contains Digital Thermal Sensors (DTS) distributed
throughout the die. These sensors are implemented as analog-to-digital converters
calibrated at the factory for reasonable accuracy to provide a digital representation of
relative processor temperature. PECI provides an interface to relay the highest DTS
temperature within a die to external management devices for thermal/fan speed
control. More detailed information may be found in Section 6.3, “Platform Environment
Control Interface (PECI)” and the RS - Platform Environment Control Interface (PECI)
Specification.
2.11.4.1 DC Characteristics
A PECI device interface operates at a nominal voltage set by V
TT
. The set of DC
electrical specifications shown in Table 2-16 is used with devices normally operating
from a V
TT
interface supply. V
TT
nominal levels will vary between processor families. All
PECI devices will operate at the V
TT
level determined by the processor installed in the
system. For specific nominal V
TT
levels, refer to Table 2-11.
Note:
1. V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications.
2. The leakage specification applies to powered devices on the PECI bus.
3. One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
Table 2-16. PECI DC Electrical Limits
Symbol
Definition and
Conditions
Min Max Units Notes
1
V
in
Input Voltage Range -0.150 V
TT
V
V
hysteresis
Hysteresis 0.1 * V
TT
N/A V
V
n
Negative-edge
threshold voltage
0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold
voltage
0.550 * V
TT
0.725 * V
TT
V
I
source
High level output
source
(V
OH
= 0.75 * V
TT
)
-6.0 N/A mA
I
sink
Low level output sink
(V
OL
= 0.25 * V
TT
)
0.5 1.0 mA
I
leak+
High impedance state
leakage to V
TT
(V
leak
= V
OL
)
N/A 50 µA 2
I
leak-
High impedance
leakage to GND
(V
leak
= V
OH
)
N/A 10 µA 2
C
bus
Bus capacitance N/A 10 pF 3
V
noise
Signal noise immunity
above 300 MHz
0.1 * V
TT
N/A V
p-p
- Datasheet 1
- Contents 3
- Revision History 7
- 1 Introduction 9
- 1.1 Terminology 11
- Introduction 12
- 1.2 State of Data 13
- 1.3 References 13
- 2 Electrical Specifications 15
- 2.2 Decoupling Guidelines 16
- Clocking 16
- 2.3.2 PLL Power Supply 18
- Electrical Specifications 20
- Table 2-4. FSB Signal Groups 21
- Asynchronous Signals 22
- 2.9 Mixing Processors 23
- Time Duration (s) 28
- Sustained Current (A) 28
- Table 2-10. V 30
- Figure 2-4. V 31
- 2.11.2 V 33
- Overshoot Specification 33
- 2.11.3 Die Voltage Validation 33
- 2.11.4.1 DC Characteristics 34
- 2.12 AGTL+ FSB Specifications 35
- Tp = T1: BCLK[1:0] period 42
- THERMTRIP# 46
- System bus 48
- FERR#/PBE# 48
- Figure 2-22. VID Step Timings 49
- 3 Mechanical Specifications 51
- Mechanical Specifications 52
- 3.7 Processor Materials 61
- 3.8 Processor Markings 62
- Processor 63
- 4 Pin Listing 65
- (Sheet 3 of 16) 66
- (Sheet 4 of 16) 66
- (Sheet 5 of 16) 67
- (Sheet 6 of 16) 67
- (Sheet 7 of 16) 68
- (Sheet 8 of 16) 68
- (Sheet 9 of 16) 69
- (Sheet 10 of 16) 69
- (Sheet 11 of 16) 70
- (Sheet 12 of 16) 70
- (Sheet 13 of 16) 71
- (Sheet 14 of 16) 71
- (Sheet 15 of 16) 72
- (Sheet 16 of 16) 72
- (Sheet 1 of 14) 73
- (Sheet 2 of 14) 73
- (Sheet 3 of 14) 74
- (Sheet 4 of 14) 74
- (Sheet 5 of 14) 75
- (Sheet 6 of 14) 75
- (Sheet 7 of 14) 76
- (Sheet 8 of 14) 76
- (Sheet 9 of 14) 77
- (Sheet 10 of 14) 77
- (Sheet 11 of 14) 78
- (Sheet 12 of 14) 78
- (Sheet 13 of 14) 79
- (Sheet 14 of 14) 79
- Pin Listing 80
- 5 Signal Definitions 81
- FSB agents 85
- . The processor includes 86
- 6 Thermal Specifications 89
- CASE_MAX 90
- CASE (°C) 91
- = 0.431 x Power + 45 95
- Power (W) 96
- Temperature (C) 96
- 6.1.2 Thermal Metrology 97
- 6.2.2 Intel Thermal Monitor 97
- 6.2.3 Intel Thermal Monitor 2 98
- 6.2.4 On-Demand Mode 99
- 6.2.5 PROCHOT# Signal 100
- 6.2.6 FORCEPR# Signal 100
- 6.2.7 THERMTRIP# Signal 100
- 6.3.1 Introduction 101
- 6.3.1.1 T 102
- 6.3.2.1 PECI Device Address 103
- 6.3.2.2 PECI Command Support 103
- 7 Features 105
- 7.2.2.1 HALT State 106
- 7.2.2.2 Extended HALT State 106
- 7.2.3 Stop-Grant State 108
- 7.3 Enhanced Intel SpeedStep 109
- Technology 109
- Features 110
- 7.4.1 SMBus Device Addressing 111
- Transactions 112
- 7.4.3.1 Header 115
- 7.4.3.2 Processor Data 119
- 0Eh-13h 120
- 7.4.3.3 Processor Core Data 121
- Offset: 1Ah-1Bh 122
- 7.4.3.4 Cache Data 124
- Offset: 29h-2Ah 125
- 2Bh-2Ch 125
- 2Dh-2Eh 125
- 7.4.3.5 Package Data 126
- 7.4.3.6 Part Number Data 127
- 38h-3Eh 128
- 3Fh-4Ch 128
- 4Dh=54h 128
- 55h-6Eh 128
- 71h-72h 129
- 7.4.3.8 Feature Data 130
- 7.4.3.9 OD: Other Data 131
- 7.4.4 Checksums 132
- 7.4.5 Scratch EEPROM 132
- 8 Debug Tools Specifications 133
- Debug Tools Specifications 134
- 9.1 Introduction 135
- 9.2 Thermal Specifications 135
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