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Features
112 Intel® Xeon® Processor 7400 Series Datasheet
Note:
1. This addressing scheme will support up to 8 processors on a single SMBus.
7.4.2 PIROM and Scratch EEPROM Supported SMBus
Transactions
The Processor Information ROM (PIROM) responds to two SMBus packet types: Read
Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge a
Write Byte command but ignore the data. The Scratch EEPROM responds to Read Byte
and Write Byte commands. Table 7-4 diagrams the Read Byte command. Table 7-5
diagrams the Write Byte command. Following a write cycle to the scratch ROM,
software must allow a minimum of 10 ms before accessing either ROM of the processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents
a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’
represents a negative acknowledge (NACK). The shaded bits are transmitted by the
Processor Information ROM or Scratch EEPROM, and the bits that aren’t shaded are
transmitted by the SMBus host controller. In the tables, the data addresses indicate 8
bits. The SMBus host controller should transmit 8 bits with the most significant bit
indicating which section of the EEPROM is to be addressed: the Processor Information
ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
Table 7-3. Memory Device SMBus Addressing
Address
(Hex)
Upper
Address
1
Device Select R/W
bits 7-4
SM_EP_A2
bit 3
SM_EP_A1
bit 2
SM_EP_A0
bit 1 bit 0
A0h/A1h1010000 X
A2h/A3h1010001 X
A4h/A5h1010010 X
A6h/A7h1010011 X
A8h/A9h1010100 X
AAh/ABh 1010 1 0 1 X
ACh/ADh1010110 X
AEh/AFh 1010 1 1 1 X
Table 7-4. Read Byte SMBus Packet
S
Slave
Addres
s
Write A
Comman
d Code
AS
Slave
Address
Read A Data /// P
17-bits 1
18-bits11 7-bits 1 1 8-bits 1 1
Table 7-5. Write Byte SMBus Packet
S Slave Address Write A Command Code ADataAP
17-bits 1
18-bits18-bits11
- Datasheet 1
- Contents 3
- Revision History 7
- 1 Introduction 9
- 1.1 Terminology 11
- Introduction 12
- 1.2 State of Data 13
- 1.3 References 13
- 2 Electrical Specifications 15
- 2.2 Decoupling Guidelines 16
- Clocking 16
- 2.3.2 PLL Power Supply 18
- Electrical Specifications 20
- Table 2-4. FSB Signal Groups 21
- Asynchronous Signals 22
- 2.9 Mixing Processors 23
- Time Duration (s) 28
- Sustained Current (A) 28
- Table 2-10. V 30
- Figure 2-4. V 31
- 2.11.2 V 33
- Overshoot Specification 33
- 2.11.3 Die Voltage Validation 33
- 2.11.4.1 DC Characteristics 34
- 2.12 AGTL+ FSB Specifications 35
- Tp = T1: BCLK[1:0] period 42
- THERMTRIP# 46
- System bus 48
- FERR#/PBE# 48
- Figure 2-22. VID Step Timings 49
- 3 Mechanical Specifications 51
- Mechanical Specifications 52
- 3.7 Processor Materials 61
- 3.8 Processor Markings 62
- Processor 63
- 4 Pin Listing 65
- (Sheet 3 of 16) 66
- (Sheet 4 of 16) 66
- (Sheet 5 of 16) 67
- (Sheet 6 of 16) 67
- (Sheet 7 of 16) 68
- (Sheet 8 of 16) 68
- (Sheet 9 of 16) 69
- (Sheet 10 of 16) 69
- (Sheet 11 of 16) 70
- (Sheet 12 of 16) 70
- (Sheet 13 of 16) 71
- (Sheet 14 of 16) 71
- (Sheet 15 of 16) 72
- (Sheet 16 of 16) 72
- (Sheet 1 of 14) 73
- (Sheet 2 of 14) 73
- (Sheet 3 of 14) 74
- (Sheet 4 of 14) 74
- (Sheet 5 of 14) 75
- (Sheet 6 of 14) 75
- (Sheet 7 of 14) 76
- (Sheet 8 of 14) 76
- (Sheet 9 of 14) 77
- (Sheet 10 of 14) 77
- (Sheet 11 of 14) 78
- (Sheet 12 of 14) 78
- (Sheet 13 of 14) 79
- (Sheet 14 of 14) 79
- Pin Listing 80
- 5 Signal Definitions 81
- FSB agents 85
- . The processor includes 86
- 6 Thermal Specifications 89
- CASE_MAX 90
- CASE (°C) 91
- = 0.431 x Power + 45 95
- Power (W) 96
- Temperature (C) 96
- 6.1.2 Thermal Metrology 97
- 6.2.2 Intel Thermal Monitor 97
- 6.2.3 Intel Thermal Monitor 2 98
- 6.2.4 On-Demand Mode 99
- 6.2.5 PROCHOT# Signal 100
- 6.2.6 FORCEPR# Signal 100
- 6.2.7 THERMTRIP# Signal 100
- 6.3.1 Introduction 101
- 6.3.1.1 T 102
- 6.3.2.1 PECI Device Address 103
- 6.3.2.2 PECI Command Support 103
- 7 Features 105
- 7.2.2.1 HALT State 106
- 7.2.2.2 Extended HALT State 106
- 7.2.3 Stop-Grant State 108
- 7.3 Enhanced Intel SpeedStep 109
- Technology 109
- Features 110
- 7.4.1 SMBus Device Addressing 111
- Transactions 112
- 7.4.3.1 Header 115
- 7.4.3.2 Processor Data 119
- 0Eh-13h 120
- 7.4.3.3 Processor Core Data 121
- Offset: 1Ah-1Bh 122
- 7.4.3.4 Cache Data 124
- Offset: 29h-2Ah 125
- 2Bh-2Ch 125
- 2Dh-2Eh 125
- 7.4.3.5 Package Data 126
- 7.4.3.6 Part Number Data 127
- 38h-3Eh 128
- 3Fh-4Ch 128
- 4Dh=54h 128
- 55h-6Eh 128
- 71h-72h 129
- 7.4.3.8 Feature Data 130
- 7.4.3.9 OD: Other Data 131
- 7.4.4 Checksums 132
- 7.4.5 Scratch EEPROM 132
- 8 Debug Tools Specifications 133
- Debug Tools Specifications 134
- 9.1 Introduction 135
- 9.2 Thermal Specifications 135
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