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Intel® Xeon® Processor 7400 Series Datasheet 49

Electrical Specifications

Notes:

1. Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion).

2. FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the

FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined

regions, the PBE# signal is driven. FERR# is driven at all other times.

Figure 2-22. VID Step Timings

Figure 2-23. VID Step Times and Vcc Waveforms

VID

n n-1 m+1m

...

Ta = T84: VID Down to Valid V

(max)

Tb = T82: VID Down to Valid V

(min)

Tc = T85: VID Up to Valid V

(max)

Td = T83: VID Up to Valid V

(min)

(max)

(min)

VID

(max)

(min)

n-1

n-2

n-3

n-4

n-6 = VID

TM2

n-1

n-2

n-3

n-4

Ta Tb

(max,n-3)

(min,n-3)

(max,n-4)

(min,n-4)

Ta = T80: VID Step Time

Tb = T81: Thermal Monitor 2 Dwell Time

Tc = T84: VID Down to Valid V

(max)

Td = T82: VID Down to Valid V

(min)

Te = T85: VID Up to Valid V

(max)

Tf = T83: VID Up to Valid V

(min)

n-5

Note: This waveform illustrates an example of an Intel Thermal

Monitor 2 transition or an Intel Enhanced SpeedStep

Technology transition that is six VID steps down from the

current state and six steps back up. Any arbitrary up or down

transition can be generalized from this waveform.

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 135 136

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