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Intel® Xeon® Processor 7400 Series Datasheet 35

Electrical Specifications

2.11.4.2 Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input

design for improved noise immunity. Use Figure 2-6 as a guide for input buffer design.

2.12 AGTL+ FSB Specifications

Routing topologies are dependent on the processors supported and the chipset used in

the design. Please refer to the appropriate platform design guidelines for specific

implementation details. In most cases, termination resistors are not required as these

are integrated into the processor silicon. See Table 2-6 for details on which signals do

not include on-die termination. Please refer to Table 2-17 for R

values.

Valid high and low levels are determined by the input buffers via comparing with a

reference voltage called GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID,

and GTLREF_ADD_END. GTLREF_DATA_MID and GTLREF_DATA_END are the reference

voltage for the FSB 4X data signals, GTLREF_ADD_MID and GTLREF_ADD_END are the

reference voltage for the FSB 2X address signals and common clock signals. Table 2-17

lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and

GTLREF_ADD_END specifications.

The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard

using high precision voltage divider circuits. Refer to the appropriate platform design

guidelines for implementation details.

Figure 2-6. Input Device Hysteresis

Minimum V

Maximum V

Minimum V

Maximum V

PECI High Range

PECI Low Range

Valid Input

Signal Range

Minimum

Hysteresis

PECI Ground

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Lenovo AD80582QH056003 Datenblatt Seite 35