Electrical Specifications
46 Intel® Xeon® Processor 7400 Series Datasheet
Note: Please refer to Table 2-12 for TAP Signal Group DC specifications and Table 2-24 for TAP Signal Group
AC specifications.
Figure 2-15. TAP Valid Delay Timing Waveform
Tx = T58: TDO Clock to Output Delay
Ts = T56: TDI, TMS Setup Time
Th = T57: TDI, TMS Hold Time
V = 0.5 * V
TT
TCK
Signal
Tx Ts Th
V Valid
V
Figure 2-16. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform
Figure 2-17. THERMTRIP# Power Down Sequence
V
T
q
T
q
T59 (TRST# Pulse Width), V = 0.5 * V
TT
T38 (PROCHOT# Pulse Width), V = GTLREF
=
THERMTRIP#
Vcc
V
TT
T
A
T
A
= T39 (THERMTRIP# to removal of power)
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