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Signal Definitions

86 Intel® Xeon® Processor 7400 Series Datasheet

PROCHOT# O PROCHOT# (Processor Hot) will go active when the processor’s temperature

monitoring sensor detects that the processor has reached its maximum safe

operating temperature. This indicates that the Thermal Control Circuit (TCC) has

been activated, if enabled. The TCC will remain active until shortly after the

processor deasserts PROCHOT#. See Section 6.2.5 for more details.

PWRGOOD I PWRGOOD (Power Good) is an input. The processor requires this signal to be a

clean indication that all processor clocks and power supplies are stable and within

their specifications. “Clean” implies that the signal will remain low (capable of

sinking leakage current), without glitches, from the time that the power supplies

are turned on until they come within specification. The signal must then transition

monotonically to a high state. Figure 2-20 illustrates the relationship of PWRGOOD

to the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks

and power must again be stable before a subsequent rising edge of PWRGOOD. It

must also meet the minimum pulse width specification in Table 2-15, and be

followed by a 1-10 ms RESET# pulse.

The PWRGOOD signal must be supplied to the processor; it is used to protect

internal circuits against voltage sequencing issues. It should be driven high

throughout boundary scan operation.

REQ[4:0]# I/O REQ[4:0]# (Request Command) must connect the appropriate pins of all processor

FSB agents. They are asserted by the current bus owner to define the currently

active transaction type. These signals are source synchronous to ADSTB[1:0]#.

Refer to the AP[1:0]# signal description for details on parity checking of these

signals.

RESET# I Asserting the RESET# signal resets all processors to known states and invalidates

their internal caches without writing back any of their contents. For a power-on

Reset, RESET# must stay active for at least 1 ms after V

CC and BCLK have reached

their proper specifications. On observing active RESET#, all FSB agents will

deassert their outputs within two clocks. RESET# must not be kept asserted for

more than 10 ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of RESET#

for power-on configuration. These configuration options are described in the

Section 7.1.

This signal does not have on-die termination and must be terminated on the

system board.

RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins of all processor FSB agents.

RSP# I RSP# (Response Parity) is driven by the response agent (the agent responsible for

completion of the current transaction) during assertion of RS[2:0]#, the signals for

which RSP# provides parity protection. It must connect to the appropriate pins of

all processor FSB agents.

A correct parity signal is high if an even number of covered signals are low and low

if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also

high, since this indicates it is not being driven by any agent guaranteeing correct

parity.

SKTOCC# O SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate

that the processor is present. There is no connection to the processor silicon for

this signal.

SM_CLK I/O The SM_CLK (SMBus Clock) signal is an input clock to the system management

logic which is required for operation of the system management features of the

processor. This clock is driven by the SMBus controller and is asynchronous to

other clocks in the processor. The processor includes a 10 kΩ pull-up resistor to

SM_VCC for this signal.

SM_DAT I/O The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal

provides the single-bit mechanism for transferring data between SMBus devices.

The processor includes a 10 kΩ pull-up resistor to SM_VCC for this signal.

SM_EP_A[2:0] I The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in

conjunction with the upper address bits in order to maintain unique addresses on

the SMBus in a system with multiple processors. To set an SM_EP_A line high, a

pull-up resistor should be used that is no larger than 1 kΩ

. The processor includes

a 10 kΩ pull-down resistor to V

for each of these signals.

SM_VCC I SM_VCC provides power to the SMBus components on the processor package.

Table 5-1. Signal Definitions (Sheet 6 of 8)

Name Type Description Notes

1 2 ... 81 82 83 84 85 86 87 88 89 90 91 ... 135 136

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