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Electrical Specifications
44 Document Number: 318080-002
Notes:
1. See Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for addition information.
2. Platform support for VID transitions is required for the processor to operate within specifications.
Notes:
1. These parameters are based on design characterization and are not tested.
2. All AC timings for the SMBus signals are referenced at V
IL_MAX
or V
IL_MIN
and measured at the
processor pins. Refer to Figure 2-23.
3. Rise time is measured from (V
IL_MAX
- 0.15V) to (V
IH_MIN
+ 0.15V). Fall time is measured
from (0.9 * SM_VCC) to (V
IL_MAX
- 0.15V). DC parameters are specified in Table 2-26.
4. Minimum time allowed between request cycles.
5. Following a write transaction, an internal write cycle time of 10ms must be allowed before
starting the next transaction.
Table 2-25. VID Signal Group AC Specifications
T # Parameter Min Max Unit Figure Notes
1, 2
T80: VID Step Time 5 µs 2-27
T81: VID Dwell Time at 266.666 MHz FSB 500 µs 2-27
T82: VID Down Transition to Valid V
CC
(min) 0 µs 2-26,2-27
T83: VID Up Transition to Valid V
CC
(min) 50 µs 2-26,2-27
T84: VID Down Transition to Valid V
CC
(max) 50 µs 2-26,2-27
T85: VID Up Transition to Valid V
CC
(max) 0 µs 2-26,2-27
Table 2-26. SMBus Signal Group AC Specifications
T# Parameter Min Max Unit Figure Notes 1, 2
T90: SM_CLK Frequency 10 100 KHz
T91: SM_CLK Period 10 100 µs
T92: SM_CLK High Time 4.0 N/A µs 2-22
T93: SM_CLK Low Time 4.7 N/A µs 2-22
T94: SMBus Rise Time 0.02 1.0 µs 2-22 3
T95: SMBus Fall Time 0.02 0.3 µs 2-22 3
T96: SMBus Output Valid Delay 0.1 4.5 µs 2-23
T97: SMBus Input Setup Time 250 N/A ns 2-22
T98: SMBus Input Hold Time 300 N/A ns 2-22
T99: Bus Free Time 4.7 N/A µs 2-22 4, 5
T100: Hold Time after Repeated Start Condition 4.0 N/A µs 2-22
T101: Repeated Start Condition Setup Time 4.7 N/A µs 2-22
T102: Stop Condition Setup Time 4.0 N/A µs 2-22
- Processor 7200 Series 1
- Contents 3
- 4 Document Number: 318080-002 4
- Document Number: 318080-002 5 5
- 6 Document Number: 318080-002 6
- Document Number: 318080-002 7 7
- Revision History 8
- 1 Introduction 9
- 1.1 Terminology 11
- Introduction 12
- 1.2 State of Data 13
- 1.3 References 13
- 2 Electrical Specifications 15
- Clocking 16
- 2.3.2 PLL Power Supply 17
- Electrical Specifications 18
- Table 2-4. FSB Signal Groups 21
- Asynchronous Signals 22
- 2.9 Mixing Processors 23
- CC_VTT_OUT 27
- Time Duration (s) 28
- Sustained Current (A) 28
- Table 2-10. V 30
- Load Lines 32
- Static and Transient 34
- Tolerance Load Lines 34
- Specifications 35
- 2.11.2.1 DC Characteristics 36
- 2.11.3 V 37
- Overshoot Specification 37
- Example Overshoot Waveform 38
- Tp = T1: BCLK[1:0] period 47
- THERMTRIP# 51
- Figure 2-26. VID Step Timings 54
- 3 Mechanical Specifications 57
- Mechanical Specifications 58
- 3.7 Processor Materials 67
- 3.8 Processor Markings 68
- Processor 69
- 4 Pin Listing 71
- 10 of 16) 75
- 11 of 16) 76
- 12 of 16) 76
- 13 of 16) 77
- 14 of 16) 77
- 15 of 16) 78
- 16 of 16) 78
- 1 of 14) 79
- 2 of 14) 79
- 3 of 14) 80
- 4 of 14) 80
- 5 of 14) 81
- 6 of 14) 81
- 8 of 14) 82
- 7 of 14) 82
- 9 of 14) 83
- 10 of 14) 83
- 11 of 14) 84
- 12 of 14) 84
- 13 of 14) 85
- 14 of 14) 85
- Pin Listing 86
- 5 Signal Definitions 87
- CC and BCLK have reached 92
- 6 Thermal Specifications 95
- CASE_MAX 96
- Thermal Profile 98
- = 0.162 x Power + 45 98
- Pow er (W) 100
- Temperature (C) 100
- = 0.420 x Power + 45 100
- = 0.238 x Power + 45 101
- 6.1.2 Thermal Metrology 102
- 6.2.2 Thermal Monitor 103
- 6.2.3 Thermal Monitor 2 104
- 6.2.4 On-Demand Mode 105
- 6.2.5 PROCHOT# Signal 106
- 6.2.6 FORCEPR# Signal 106
- 6.2.7 THERMTRIP# Signal 106
- 6.3.1 Introduction 107
- 6.3.2 PECI Specifications 108
- 7 Features 111
- 7.2.1 Normal State 112
- EXTENDED_HALT 113
- 7.2.3 Stop-Grant State 114
- 7.3 Enhanced Intel SpeedStep 115
- Technology 115
- Features 116
- 7.4.1 SMBus Device Addressing 117
- Transactions 118
- 7.4.3.1 Header 121
- 7.4.3.2 Processor Data 125
- 7.4.3.3 Processor Core Data 126
- 16h-19h 127
- 1Ah-1Bh 127
- Offset: 1Ch 128
- 1Dh-1Eh 128
- 1Fh-20h 128
- 7.4.3.4 Cache Data 129
- 7.4.3.5 Package Data 131
- 7.4.3.6 Part Number Data 132
- 38h-3Eh 133
- 3Fh-4Ch 133
- 4Dh=54h 133
- 55h-6Eh 134
- 71h-72h 134
- 7.4.3.8 Feature Data 135
- 7.4.3.9 Other Data 136
- 7.4.4 Checksums 137
- 7.4.5 Scratch EEPROM 137
- 8.1 Introduction 139
- 8.2 Thermal Specifications 139
- 9 Debug Tools Specifications 141
- Debug Tools Specifications 142
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