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Electrical Specifications
36 Document Number: 318080-002
7300 Series contains Digital Thermal Sensors (DTS) distributed throughout the die.
These sensors are implemented as analog-to-digital converters calibrated at the factory
for reasonable accuracy to provide a digital representation of relative processor
temperature. PECI provides an interface to relay the highest DTS temperature within a
die to external management devices for thermal/fan speed control.
2.11.2.1 DC Characteristics
A PECI device interface operates at a nominal voltage set by V
TT
. The set of DC
electrical specifications shown in Table 2-15 is used with devices normally operating
from a V
TT
interface supply. V
TT
nominal levels will vary between processor families. All
PECI devices will operate at the V
TT
level determined by the processor installed in the
system. For specific nominal V
TT
levels, refer to Table 2-11.
Note:
1. V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications.
2. The leakage specification applies to powered devices on the PECI bus.
3. One node is counted for each client and one node for the system host. Extended trace lengths might
appear as additional nodes.
2.11.2.2 Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 2-9 as a guide for input buffer design.
Table 2-15. PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes
1
V
in
Input Voltage Range
-0.150 V
TT
V
V
hysteresis
Hysteresis
0.1 * V
TT
N/A V
V
n
Negative-edge threshold voltage
0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold voltage
0.550 * V
TT
0.762 * V
TT
V
I
source
High level output source
(V
OH
= 0.75 * V
TT
)
-6.0 N/A mA
I
sink
Low level output sink
(V
OL
= 0.25 * V
TT
)
0.5 1.0 mA
I
leak+
High impedance state leakage to V
TT
(V
leak
= V
OL
)
N/A 50 µA 2
I
leak-
High impedance leakage to GND
(V
leak
= V
OH
)
N/A 10 µA 2
C
bus
Bus capacitance
N/A 10 pF 3
V
noise
Signal noise immunity above 300 MHz
0.1 * V
TT
N/A V
p-p
- Processor 7200 Series 1
- Contents 3
- 4 Document Number: 318080-002 4
- Document Number: 318080-002 5 5
- 6 Document Number: 318080-002 6
- Document Number: 318080-002 7 7
- Revision History 8
- 1 Introduction 9
- 1.1 Terminology 11
- Introduction 12
- 1.2 State of Data 13
- 1.3 References 13
- 2 Electrical Specifications 15
- Clocking 16
- 2.3.2 PLL Power Supply 17
- Electrical Specifications 18
- Table 2-4. FSB Signal Groups 21
- Asynchronous Signals 22
- 2.9 Mixing Processors 23
- CC_VTT_OUT 27
- Time Duration (s) 28
- Sustained Current (A) 28
- Table 2-10. V 30
- Load Lines 32
- Static and Transient 34
- Tolerance Load Lines 34
- Specifications 35
- 2.11.2.1 DC Characteristics 36
- 2.11.3 V 37
- Overshoot Specification 37
- Example Overshoot Waveform 38
- Tp = T1: BCLK[1:0] period 47
- THERMTRIP# 51
- Figure 2-26. VID Step Timings 54
- 3 Mechanical Specifications 57
- Mechanical Specifications 58
- 3.7 Processor Materials 67
- 3.8 Processor Markings 68
- Processor 69
- 4 Pin Listing 71
- 10 of 16) 75
- 11 of 16) 76
- 12 of 16) 76
- 13 of 16) 77
- 14 of 16) 77
- 15 of 16) 78
- 16 of 16) 78
- 1 of 14) 79
- 2 of 14) 79
- 3 of 14) 80
- 4 of 14) 80
- 5 of 14) 81
- 6 of 14) 81
- 8 of 14) 82
- 7 of 14) 82
- 9 of 14) 83
- 10 of 14) 83
- 11 of 14) 84
- 12 of 14) 84
- 13 of 14) 85
- 14 of 14) 85
- Pin Listing 86
- 5 Signal Definitions 87
- CC and BCLK have reached 92
- 6 Thermal Specifications 95
- CASE_MAX 96
- Thermal Profile 98
- = 0.162 x Power + 45 98
- Pow er (W) 100
- Temperature (C) 100
- = 0.420 x Power + 45 100
- = 0.238 x Power + 45 101
- 6.1.2 Thermal Metrology 102
- 6.2.2 Thermal Monitor 103
- 6.2.3 Thermal Monitor 2 104
- 6.2.4 On-Demand Mode 105
- 6.2.5 PROCHOT# Signal 106
- 6.2.6 FORCEPR# Signal 106
- 6.2.7 THERMTRIP# Signal 106
- 6.3.1 Introduction 107
- 6.3.2 PECI Specifications 108
- 7 Features 111
- 7.2.1 Normal State 112
- EXTENDED_HALT 113
- 7.2.3 Stop-Grant State 114
- 7.3 Enhanced Intel SpeedStep 115
- Technology 115
- Features 116
- 7.4.1 SMBus Device Addressing 117
- Transactions 118
- 7.4.3.1 Header 121
- 7.4.3.2 Processor Data 125
- 7.4.3.3 Processor Core Data 126
- 16h-19h 127
- 1Ah-1Bh 127
- Offset: 1Ch 128
- 1Dh-1Eh 128
- 1Fh-20h 128
- 7.4.3.4 Cache Data 129
- 7.4.3.5 Package Data 131
- 7.4.3.6 Part Number Data 132
- 38h-3Eh 133
- 3Fh-4Ch 133
- 4Dh=54h 133
- 55h-6Eh 134
- 71h-72h 134
- 7.4.3.8 Feature Data 135
- 7.4.3.9 Other Data 136
- 7.4.4 Checksums 137
- 7.4.5 Scratch EEPROM 137
- 8.1 Introduction 139
- 8.2 Thermal Specifications 139
- 9 Debug Tools Specifications 141
- Debug Tools Specifications 142
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