Lenovo LF80565QH0254M Datenblatt Seite 126

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Features
126 Document Number: 318080-002
7.4.3.2.2 SAMPROD: Sample/Production
This location contains the sample/production field, which is a two-bit field and is LSB
aligned. All S-spec material will use a value of 01b. All other values are reserved.
Writes to this register have no effect.
Example: A processor with an Sxxxx mark (production unit) will use 01h at offset
14h.
7.4.3.2.3 PDCKS: Processor Data Checksum
This location provides the checksum of the Processor Data Section. Writes to this
register have no effect.
7.4.3.3 Processor Core Data
This section contains core silicon-related data.
7.4.3.3.1 CPUID: CPUID
This location contains the CPUID, Processor Type, Family, Model and Stepping. The
CPUID field is a copy of the results in EAX[27:0] from Function 1 of the CPUID
instruction. The MSB is at location 16h, the LSB is at location 19h. Writes to this
register have no effect.
Note: The field is not aligned on a byte boundary since the first two bits of the offset are
reserved. Thus, the data must be shifted left by two in order to obtain the same
results.
Example: The CPUID of a G-0 stepping Intel
®
Xeon
®
Processor 7200 Series and 7300
Series is 06FBh. The value programmed into the PIROM is 00001BECh.
Note: The first two bits of the PIROM are reserved, as highlighted in the example below.
CPUID instruction results 0000 0110 1111 1011 (06F9h)
PIROM content 0001 1011 1110 1100 (1BECh)
Offset: 14h
Bit Description
7:2 RESERVED
000000b-111111b: Reserved
1:0 Sample/Production
Sample or Production indictor
00b: Sample
01b: Production
10b-11b: Reserved
Offset: 15h
Bit Description
7:0 Processor Data Checksum
One Byte Checksum of the of Processor Data Section
00h- FFh: See Section 7.4.4 for calculation of the value
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