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Electrical Specifications

38 Document Number: 318080-002

Notes:

1. VOS is the measured overshoot voltage.

2. TOS is the measured time duration above VID.

2.11.3.1 Die Voltage Validation

Core voltage (VCC) overshoot events at the processor must meet the specifications in

Table 2-16 when measured across the VCC_SENSE and VSS_SENSE pins and across

the VCC_SENSE2 and VSS_SENSE2 pins. Overshoot events that are < 10 ns in duration

may be ignored. These measurements of processor die level overshoot should be taken

with a 100 MHz bandwidth limited oscilloscope.

2.11.4 AGTL+ FSB Specifications

Routing topologies are dependent on the processors supported and the chipset used in

the design. Please refer to the appropriate platform design guidelines for specific

implementation details. In most cases, termination resistors are not required as these

are integrated into the processor silicon. See Table 2-6 for details on which signals do

not include on-die termination. Please refer to Table 2-17 for R

values.

Valid high and low levels are determined by the input buffers via comparing with a

reference voltage called GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID,

and GTLREF_ADD_END. GTLREF_DATA_MID and GTLREF_DATA_END are the reference

voltage for the FSB 4X data signals, GTLREF_ADD_MID and GTLREF_ADD_END are the

reference voltage for the FSB 2X address signals and common clock signals. Table 2-17

lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and

GTLREF_ADD_END specifications.

The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard

using high precision voltage divider circuits. Refer to the appropriate platform design

guidelines for implementation details.

Figure 2-10. V

Overshoot Example Waveform

Example Overshoot Waveform

0 5 10 15 20 25

Time [us]

Voltage [V]

VID - 0.000

VID + 0.050

: Overshoot time above VID

: Overshoot above VID

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 141 142

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