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Thermal Specifications
108 Document Number: 318080-002
6.3.1.2 Processor Thermal Data Sample Rate and Filtering
The DTS (Digital Thermal Sensors) provide an improved capability to monitor device
hot spots, which inherently leads to more varying temperature readings over short
time intervals. The DTS sample interval range can be modified, and a data filtering
algorithm can be activated to help moderate this. The DTS sample interval range is 82
us (default) to 20 ms (max). This value can be set in BIOS.
To reduce the sample rate requirements on PECI and improve thermal data stability vs.
time the processor DTS also implements an averaging algorithm that filters the
incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed
mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) +
(new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on
by default and can be turned off in BIOS.
Host controllers should utilize the min/max sample times to determine the appropriate
sample rate based on the controller's fan control algorithm and targeted response rate.
The key items to take into account when settling on a fan control algorithm are the DTS
sample rate, whether the temperature filter is enabled, how often the PECI host will
poll the processor for temperature data, and the rate at which fan speed is changed.
Depending on the designer’s specific requirements the DTS sample rate and alpha-beta
filter may have no effect on the fan control algorithm.
6.3.2 PECI Specifications
6.3.2.1 PECI Device Address
The Intel
®
Xeon
®
Processor 7200 Series and 7300 Series obtains its PECI address
based on the processor APIC ID[4:2] at power on. APIC ID[4:3] is also known as
Cluster ID[1:0] and APIC ID[2] is also known as Agent ID[1]. Cluster ID[1:0] is set by
the chipset driven power-on configuration (POC) signals A[12:11]#. Table 6-9 shows
how the Agent ID is generated for each of the die based on the BREQ# signals asserted
during power on for the Intel
®
Xeon
®
Processor 7200 Series and 7300 Series.
Figure 6-8. Conceptual Fan Control Diagram For a PECI-Based Platform
Fan Speed
(RPM)
(not intended to depict actual implementation)
Max
Min
Temperature
PECI = -10
PECI = -20
TCC Activation
Temperature
T
CONTROL
Setting
PECI = 0
Fan Speed
(RPM)
(not intended to depict actual implementation)
Max
Min
Temperature
PECI = -10
PECI = -20
TCC Activation
Temperature
T
CONTROL
Setting
PECI = 0
- Processor 7200 Series 1
- Contents 3
- 4 Document Number: 318080-002 4
- Document Number: 318080-002 5 5
- 6 Document Number: 318080-002 6
- Document Number: 318080-002 7 7
- Revision History 8
- 1 Introduction 9
- 1.1 Terminology 11
- Introduction 12
- 1.2 State of Data 13
- 1.3 References 13
- 2 Electrical Specifications 15
- Clocking 16
- 2.3.2 PLL Power Supply 17
- Electrical Specifications 18
- Table 2-4. FSB Signal Groups 21
- Asynchronous Signals 22
- 2.9 Mixing Processors 23
- CC_VTT_OUT 27
- Time Duration (s) 28
- Sustained Current (A) 28
- Table 2-10. V 30
- Load Lines 32
- Static and Transient 34
- Tolerance Load Lines 34
- Specifications 35
- 2.11.2.1 DC Characteristics 36
- 2.11.3 V 37
- Overshoot Specification 37
- Example Overshoot Waveform 38
- Tp = T1: BCLK[1:0] period 47
- THERMTRIP# 51
- Figure 2-26. VID Step Timings 54
- 3 Mechanical Specifications 57
- Mechanical Specifications 58
- 3.7 Processor Materials 67
- 3.8 Processor Markings 68
- Processor 69
- 4 Pin Listing 71
- 10 of 16) 75
- 11 of 16) 76
- 12 of 16) 76
- 13 of 16) 77
- 14 of 16) 77
- 15 of 16) 78
- 16 of 16) 78
- 1 of 14) 79
- 2 of 14) 79
- 3 of 14) 80
- 4 of 14) 80
- 5 of 14) 81
- 6 of 14) 81
- 8 of 14) 82
- 7 of 14) 82
- 9 of 14) 83
- 10 of 14) 83
- 11 of 14) 84
- 12 of 14) 84
- 13 of 14) 85
- 14 of 14) 85
- Pin Listing 86
- 5 Signal Definitions 87
- CC and BCLK have reached 92
- 6 Thermal Specifications 95
- CASE_MAX 96
- Thermal Profile 98
- = 0.162 x Power + 45 98
- Pow er (W) 100
- Temperature (C) 100
- = 0.420 x Power + 45 100
- = 0.238 x Power + 45 101
- 6.1.2 Thermal Metrology 102
- 6.2.2 Thermal Monitor 103
- 6.2.3 Thermal Monitor 2 104
- 6.2.4 On-Demand Mode 105
- 6.2.5 PROCHOT# Signal 106
- 6.2.6 FORCEPR# Signal 106
- 6.2.7 THERMTRIP# Signal 106
- 6.3.1 Introduction 107
- 6.3.2 PECI Specifications 108
- 7 Features 111
- 7.2.1 Normal State 112
- EXTENDED_HALT 113
- 7.2.3 Stop-Grant State 114
- 7.3 Enhanced Intel SpeedStep 115
- Technology 115
- Features 116
- 7.4.1 SMBus Device Addressing 117
- Transactions 118
- 7.4.3.1 Header 121
- 7.4.3.2 Processor Data 125
- 7.4.3.3 Processor Core Data 126
- 16h-19h 127
- 1Ah-1Bh 127
- Offset: 1Ch 128
- 1Dh-1Eh 128
- 1Fh-20h 128
- 7.4.3.4 Cache Data 129
- 7.4.3.5 Package Data 131
- 7.4.3.6 Part Number Data 132
- 38h-3Eh 133
- 3Fh-4Ch 133
- 4Dh=54h 133
- 55h-6Eh 134
- 71h-72h 134
- 7.4.3.8 Feature Data 135
- 7.4.3.9 Other Data 136
- 7.4.4 Checksums 137
- 7.4.5 Scratch EEPROM 137
- 8.1 Introduction 139
- 8.2 Thermal Specifications 139
- 9 Debug Tools Specifications 141
- Debug Tools Specifications 142
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