Lenovo LF80565QH0254M Datenblatt Seite 128

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Features
128 Document Number: 318080-002
7.4.3.3.3 MPSUP: Multiprocessor Support
This location contains 2 bits for representing the supported number of physical
processors on the bus. These two bits are MSB aligned where 00b equates to single-
processor operation, 01b is a dual-processor operation, and 11b represents multi-
processor operation. The Intel
®
Xeon
®
Processor 7200 Series and 7300 Series is an MP
processor. The remaining six bits in this field are reserved for the future use. Writes to
this register have no effect.
Example: An MP processor will use C0h at offset 1Ch.
7.4.3.3.4 MCF: Maximum Core Frequency
This location contains the maximum core frequency for the processor. Format of this
field is in MHz, rounded to a whole number, and encoded in hex format. Writes to this
register have no effect.
Example: A 2.666 GHz processor will have a value of 0A6Ah, which equates to 2666
decimal.
7.4.3.3.5 MAXVID: Maximum Core VID
This location contains the maximum Core VID (Voltage Identification) voltage that may
be requested via the VID pins. This field, rounded to the next thousandth, is in mV and
is reflected in hex. Writes to this register have no effect.
Example: A voltage of 1.350 V maximum core VID would contain 0546h (1350
decimal) in Offset 1F - 20h.
Offset: 1Ch
Bit Description
7:6 Multiprocessor Support
UP, DP or MP indictor
00b: UP
01b: DP
10b: Reserved
11b: MP
5:0 RESERVED
000000b-111111b: Reserved
Offset: 1Dh-1Eh
Bit Description
15:0 Maximum Core Frequency
0000h-FFFFh: MHz
Offset: 1Fh-20h
Bit Description
15:0 Maximum Core VID
0000h-FFFFh: mV
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