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Document Number: 318080-002 121
Features
Details on each of these sections are described below.
Note: Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not
rely on this model.
7.4.3.1 Header
To maintain backward compatibility, the Header defines the starting address for each
subsequent section of the PIROM. Software should check for the offset before reading
data from a particular section of the ROM.
Example: Code looking for the cache data of a processor would read offset 05h to find
a value of 25h. 25h is the first address within the 'Cache Data' section of the PIROM.
7.4.3.1.1 DFR: Data Format Revision
This location identifies the data format revision of the PIROM data structure. Writes to
this register have no effect.
78h 8 Processor Feature Flags [7] = Multi-Core
[6] = Serial Signature
[5] = Electronic Signature Present
[4] = Thermal Sense Device Present
[3] = Reserved
[2] = OEM EEPROM Present
[1] = Core VID Present
[0] = L3 Cache Present
79h 8 Processor Thread and Core
Information
[7:2] = Number of cores
[1:0] = Number of threads per core
7Ah 8 Additional Processor Feature
Flags
[7] = Reserved
[6] = Intel
®
Cache Safe Technology
[5] = Extended Halt State (C1E)
[4] = Intel
®
Virtualization Technology
[3] = Execute Disable
[2] = Intel
®
64
[1] = Thermal Monitor TM2
[0] = Enhanced Intel
®
SpeedStep
®
Technology
7B-7Ch 16 Thermal Adjustment Factors
(Pending)
[15:8] = Measurement Correction Factor
[7:0] = Temperature Target
7D-7Eh 16 Reserved Reserved
7Fh 8 Checksum 1 byte checksum
Table 7-6. Processor Information ROM Data Sections (Sheet 3 of 3)
Offset/Section
# of
Bits
Function Notes
Offset: 00h
Bit Description
7:0 Data Format Revision
The data format revision is used whenever fields within the PIROM are
redefined. The initial definition will begin at a value of 1. If a field, or bit
assignment within a field, is changed such that software needs to discern
between the old and new definition, then the data format revision field will be
incremented.
00h: Reserved
01h: Initial definition
02h: Second revision
03h: Third revision
04h: Fourth revision (Defined by this document)
05h-FFh: Reserved
- Processor 7200 Series 1
- Contents 3
- 4 Document Number: 318080-002 4
- Document Number: 318080-002 5 5
- 6 Document Number: 318080-002 6
- Document Number: 318080-002 7 7
- Revision History 8
- 1 Introduction 9
- 1.1 Terminology 11
- Introduction 12
- 1.2 State of Data 13
- 1.3 References 13
- 2 Electrical Specifications 15
- Clocking 16
- 2.3.2 PLL Power Supply 17
- Electrical Specifications 18
- Table 2-4. FSB Signal Groups 21
- Asynchronous Signals 22
- 2.9 Mixing Processors 23
- CC_VTT_OUT 27
- Time Duration (s) 28
- Sustained Current (A) 28
- Table 2-10. V 30
- Load Lines 32
- Static and Transient 34
- Tolerance Load Lines 34
- Specifications 35
- 2.11.2.1 DC Characteristics 36
- 2.11.3 V 37
- Overshoot Specification 37
- Example Overshoot Waveform 38
- Tp = T1: BCLK[1:0] period 47
- THERMTRIP# 51
- Figure 2-26. VID Step Timings 54
- 3 Mechanical Specifications 57
- Mechanical Specifications 58
- 3.7 Processor Materials 67
- 3.8 Processor Markings 68
- Processor 69
- 4 Pin Listing 71
- 10 of 16) 75
- 11 of 16) 76
- 12 of 16) 76
- 13 of 16) 77
- 14 of 16) 77
- 15 of 16) 78
- 16 of 16) 78
- 1 of 14) 79
- 2 of 14) 79
- 3 of 14) 80
- 4 of 14) 80
- 5 of 14) 81
- 6 of 14) 81
- 8 of 14) 82
- 7 of 14) 82
- 9 of 14) 83
- 10 of 14) 83
- 11 of 14) 84
- 12 of 14) 84
- 13 of 14) 85
- 14 of 14) 85
- Pin Listing 86
- 5 Signal Definitions 87
- CC and BCLK have reached 92
- 6 Thermal Specifications 95
- CASE_MAX 96
- Thermal Profile 98
- = 0.162 x Power + 45 98
- Pow er (W) 100
- Temperature (C) 100
- = 0.420 x Power + 45 100
- = 0.238 x Power + 45 101
- 6.1.2 Thermal Metrology 102
- 6.2.2 Thermal Monitor 103
- 6.2.3 Thermal Monitor 2 104
- 6.2.4 On-Demand Mode 105
- 6.2.5 PROCHOT# Signal 106
- 6.2.6 FORCEPR# Signal 106
- 6.2.7 THERMTRIP# Signal 106
- 6.3.1 Introduction 107
- 6.3.2 PECI Specifications 108
- 7 Features 111
- 7.2.1 Normal State 112
- EXTENDED_HALT 113
- 7.2.3 Stop-Grant State 114
- 7.3 Enhanced Intel SpeedStep 115
- Technology 115
- Features 116
- 7.4.1 SMBus Device Addressing 117
- Transactions 118
- 7.4.3.1 Header 121
- 7.4.3.2 Processor Data 125
- 7.4.3.3 Processor Core Data 126
- 16h-19h 127
- 1Ah-1Bh 127
- Offset: 1Ch 128
- 1Dh-1Eh 128
- 1Fh-20h 128
- 7.4.3.4 Cache Data 129
- 7.4.3.5 Package Data 131
- 7.4.3.6 Part Number Data 132
- 38h-3Eh 133
- 3Fh-4Ch 133
- 4Dh=54h 133
- 55h-6Eh 134
- 71h-72h 134
- 7.4.3.8 Feature Data 135
- 7.4.3.9 Other Data 136
- 7.4.4 Checksums 137
- 7.4.5 Scratch EEPROM 137
- 8.1 Introduction 139
- 8.2 Thermal Specifications 139
- 9 Debug Tools Specifications 141
- Debug Tools Specifications 142
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