Lenovo LF80565QH0254M Datenblatt PDF herunterladen (Seite 39)

Document Number: 318080-002 39

Electrical Specifications

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values

across the range of V

3. GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from V

on the

baseboard by a voltage divider of 1% resistors. The minimum and maximum specifications account for this resistor tolerance.

Refer to the appropriate platform design guidelines for implementation details. The V

referred to in these specifications is

the instantaneous V

4. R

is the on-die termination resistance measured at V

of the AGTL+ output driver. Measured at 0.31*V

. R

is connected

to V

on die. Refer to processor I/O Buffer Models for I/V characteristics.

5. COMP resistance must be provided on the system board with +/- 1% resistors. See the applicable platform design guide for

implementation details.

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of

BCLK1.

3. V

Havg

is the statistical average of the V

measured by the oscilloscope.

4. Overshoot is defined as the absolute value of the maximum voltage.

5. Undershoot is defined as the absolute value of the minimum voltage.

6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum

Falling Edge Ringback.

7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches.

It includes input threshold hysteresis.

8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

9. V

Havg

can be measured directly using “Vtop” on Agilent and “High” on Tektronix oscilloscopes.

10. For V

between 0 V and V

ΔV

CROSS

is defined as the total variation of all crossing voltages as defined in note 2.

Table 2-17. AGTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

GTLREF_DATA_MID

GTLREF_DATA_END

Data Bus Reference

Voltage

0.98 * 0.67 * V

0.67 * V

1.02 * 0.67 * V

V2, 3

GTLREF_ADD_MID

GTLREF_ADD_END

Address Bus

Reference Voltage

0.98 * 0.67 * V

0.67 * V

1.02 * 0.67 * V

V2, 3

Termination

Resistance (pull up)

45 50 55

COMP COMP Resistance 49.4 49.9 50.4

Table 2-18. FSB Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes

1,2

Single-ended Input

Low Voltage

-0.150 0.0 0.15 V 2-13

Single-ended Input

High Voltage

0.660 0.710 0.850 V 2-13

CROSS(abs)

Absolute Crossing

Point

0.250 0.350 0.550 V 2-13,

2-14

2,8

CROSS(rel)

Relative Crossing

Point

0.250 +

0.5 * (V

Havg

- 0.700)

N/A 0.550 +

0.5 * (V

Havg

- 0.700)

V 2-13,

2-14

3,8,9, 11

Δ V

CROSS

Vcross variation N/A N/A 0.140 V 2-13,

2-14

MAX (Absolute

Overshoot)

Single-ended

maximum voltage

N/A N/A 1.15 V 2-13 4

MIN (Absolute

Undershoot)

Single-ended

minimum voltage

-0.300 N/A N/A V 2-13 5

RBM

Single-ended

Ringback Margin

0.200 N/A N/A V 2-13 6

Single-ended

Threshold Region

CROSS

- 0.100 N/A V

CROSS

+ 0.100 V 2-13 7

Input Leakage

Current

N/A N/A +/- 100 μA10

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 141 142

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