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Electrical Specifications
36 Intel® Xeon® Processor 7400 Series Datasheet
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values
across the range of V
TT
.
3. GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from V
TT
on the baseboard
by a voltage divider of 1% resistors. The minimum and maximum specifications account for this resistor tolerance. Refer to
the appropriate platform design guidelines for implementation details. The V
TT
referred to in these specifications is the
instantaneous V
TT
4. R
TT
is the on-die termination resistance measured at V
OL
of the AGTL+ output driver. Measured at 0.33*V
TT
. R
TT
is connected
to V
TT
on die.
5. COMP resistance must be provided on the system board with +/- 1% resistors. See the applicable platform design guide for
implementation details
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of
BCLK1.
3. V
Havg
is the statistical average of the V
H
measured by the oscilloscope.
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum
Falling Edge Ringback.
7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches.
It includes input threshold hysteresis.
8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
9. V
Havg
can be measured directly using “Vtop” on Agilent* and “High” on Tektronix* oscilloscopes.
10. For VIN between 0 V and VH,
11. VCROSS is defined as the total variation of all crossing voltages as defined in note 3.
Table 2-17. AGTL+ Bus Voltage Definitions
Symbol Parameter Min Typ Max Units Notes
1
GTLREF_DATA_MID
GTLREF_DATA_END
Data Bus Reference
Voltage
0.98 * 0.67 * V
TT
0.67 * V
TT
1.02 * 0.67 * V
TT
V2, 3
GTLREF_ADD_MID
GTLREF_ADD_END
Address Bus
Reference Voltage
0.98 * 0.67 * V
TT
0.67 * V
TT
1.02 * 0.67 * V
TT
V2, 3
R
TT
Termination
Resistance (pull up)
45 50 55
Ω
4
COMP COMP Resistance 49.4 49.9 50.4
Ω
5
Table 2-18. FSB Differential BCLK Specifications
Symbol Parameter Min Typ Max Unit Figure Notes
1
V
L
Input Low Voltage -0.150 0.0 .15 V 2-9
V
H
Input High Voltage 0.660 0.710 0.850 V 2-9
V
CROSS(abs)
Absolute Crossing
Point
0.250 0.350 0.550 V 2-9, 2-10 2,8
V
CROSS(rel)
Relative Crossing
Point
0.250 +
0.5 * (V
Havg
- 0.700)
N/A 0.550 +
0.5 * (V
Havg
- 0.700)
V 2-9, 2-10 3,8,9,11
Δ V
CROSS
Range of Crossing
Points
N/A N/A 0.140 V 2-9, 2-10
V
OS
Overshoot N/A N/A V
H
+ 0.300 V 2-9 4
V
US
Undershoot -0.300 N/A N/A V 2-9 5
V
RBM
Ringback Margin 0.200 N/A N/A V 2-9 6
V
TR
Threshold Region V
CROSS
- 0.100 N/A V
CROSS
+ 0.100 V 2-9 7
I
LI
Input Leakage
Current
N/A N/A +/- 100 μA10
- Datasheet 1
- Contents 3
- Revision History 7
- 1 Introduction 9
- 1.1 Terminology 11
- Introduction 12
- 1.2 State of Data 13
- 1.3 References 13
- 2 Electrical Specifications 15
- 2.2 Decoupling Guidelines 16
- Clocking 16
- 2.3.2 PLL Power Supply 18
- Electrical Specifications 20
- Table 2-4. FSB Signal Groups 21
- Asynchronous Signals 22
- 2.9 Mixing Processors 23
- Time Duration (s) 28
- Sustained Current (A) 28
- Table 2-10. V 30
- Figure 2-4. V 31
- 2.11.2 V 33
- Overshoot Specification 33
- 2.11.3 Die Voltage Validation 33
- 2.11.4.1 DC Characteristics 34
- 2.12 AGTL+ FSB Specifications 35
- Tp = T1: BCLK[1:0] period 42
- THERMTRIP# 46
- System bus 48
- FERR#/PBE# 48
- Figure 2-22. VID Step Timings 49
- 3 Mechanical Specifications 51
- Mechanical Specifications 52
- 3.7 Processor Materials 61
- 3.8 Processor Markings 62
- Processor 63
- 4 Pin Listing 65
- (Sheet 3 of 16) 66
- (Sheet 4 of 16) 66
- (Sheet 5 of 16) 67
- (Sheet 6 of 16) 67
- (Sheet 7 of 16) 68
- (Sheet 8 of 16) 68
- (Sheet 9 of 16) 69
- (Sheet 10 of 16) 69
- (Sheet 11 of 16) 70
- (Sheet 12 of 16) 70
- (Sheet 13 of 16) 71
- (Sheet 14 of 16) 71
- (Sheet 15 of 16) 72
- (Sheet 16 of 16) 72
- (Sheet 1 of 14) 73
- (Sheet 2 of 14) 73
- (Sheet 3 of 14) 74
- (Sheet 4 of 14) 74
- (Sheet 5 of 14) 75
- (Sheet 6 of 14) 75
- (Sheet 7 of 14) 76
- (Sheet 8 of 14) 76
- (Sheet 9 of 14) 77
- (Sheet 10 of 14) 77
- (Sheet 11 of 14) 78
- (Sheet 12 of 14) 78
- (Sheet 13 of 14) 79
- (Sheet 14 of 14) 79
- Pin Listing 80
- 5 Signal Definitions 81
- FSB agents 85
- . The processor includes 86
- 6 Thermal Specifications 89
- CASE_MAX 90
- CASE (°C) 91
- = 0.431 x Power + 45 95
- Power (W) 96
- Temperature (C) 96
- 6.1.2 Thermal Metrology 97
- 6.2.2 Intel Thermal Monitor 97
- 6.2.3 Intel Thermal Monitor 2 98
- 6.2.4 On-Demand Mode 99
- 6.2.5 PROCHOT# Signal 100
- 6.2.6 FORCEPR# Signal 100
- 6.2.7 THERMTRIP# Signal 100
- 6.3.1 Introduction 101
- 6.3.1.1 T 102
- 6.3.2.1 PECI Device Address 103
- 6.3.2.2 PECI Command Support 103
- 7 Features 105
- 7.2.2.1 HALT State 106
- 7.2.2.2 Extended HALT State 106
- 7.2.3 Stop-Grant State 108
- 7.3 Enhanced Intel SpeedStep 109
- Technology 109
- Features 110
- 7.4.1 SMBus Device Addressing 111
- Transactions 112
- 7.4.3.1 Header 115
- 7.4.3.2 Processor Data 119
- 0Eh-13h 120
- 7.4.3.3 Processor Core Data 121
- Offset: 1Ah-1Bh 122
- 7.4.3.4 Cache Data 124
- Offset: 29h-2Ah 125
- 2Bh-2Ch 125
- 2Dh-2Eh 125
- 7.4.3.5 Package Data 126
- 7.4.3.6 Part Number Data 127
- 38h-3Eh 128
- 3Fh-4Ch 128
- 4Dh=54h 128
- 55h-6Eh 128
- 71h-72h 129
- 7.4.3.8 Feature Data 130
- 7.4.3.9 OD: Other Data 131
- 7.4.4 Checksums 132
- 7.4.5 Scratch EEPROM 132
- 8 Debug Tools Specifications 133
- Debug Tools Specifications 134
- 9.1 Introduction 135
- 9.2 Thermal Specifications 135
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