Lenovo x3400 M3 Betriebsanweisung PDF herunterladen (Seite 5)

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DDR-3 Registered Memory with Chipkill ECC Protection

The x3400 M3 ships with registered double data rate III (DDR-3) memory and provides Active

Memory features, including advanced Chipkill memory protection (optionally), for up to 16X better

error correction than standard ECC memory. In addition to offering better performance than DDR-2

or fully-buffered memory, DDR-3 memory also uses less energy. DDR-2 memory already offered up

to 37% lower energy use than fully buffered memory. Now, a generation later, DDR-3 memory is

even more efficient, using 22% less energy than DDR-2 memory.

The x3400 M3 supports up to 128GB of RDIMM (registered DIMM) memory in 16 DIMM slots, or up

to 48GB of UDIMM (unbuffered DIMM) memory in 12 slots. Redesign in the architecture of the Xeon

5600 series processors bring radical changes in the way memory works in these servers. For

example, the Xeon 5600 series processor integrates the memory controller inside the processor,

resulting in two memory controllers in a 2-socket system. Each memory controller has three memory

channels. Depending on the type of memory, population of memory, and processor model, the

memory may be clocked at 1066MHz or 1333Mhz.

Note: If only one processor is installed, only the first eight DIMM slots can be used. Adding a second

processor not only doubles the amount of memory available for use, but also doubles the number of

memory controllers, thus doubling the system memory bandwidth. If you add a second processor,

but no additional memory for the second processor, the second processor has to access the memory

from the first processor “remotely,” resulting in longer latencies and lower performance. The latency

to access remote memory is almost 75% higher than local memory access. So, the goal should be to

always populate both processors with memory.

The E5603, E5606, E5607, and E5620 processors support up to 1066MHz clock speed. Using

1066MHz memory (where supported) versus 800MHz offers up to 28% better performance. X5650

through X5675 processors, supporting up to 1333MHz clock speed, are available via CTO,

Xeon 5600 series processors access memory with almost 50% lower latency than the earlier 5400

series processors. That can result in faster processing of latency-sensitive workloads.

This new processor design comes with some trade-offs in memory capacity, performance, and cost:

For example, greater memory capacity comes with lower memory speed. Alternatively, it is

possible to achieve the same memory capacity at lower cost but at a lower memory speed.

Regardless of memory speed, the Xeon 5600 platform represents a significant improvement in

memory bandwidth over the previous Xeon 5400 platform. This improvement is mainly due to the

dual integrated memory controllers and faster DDR-3 memory. Throughput at 800MHz is 25

gigabytes per second (GBps); at 1066MHz it’s 32GBps; and at 1333MHz it’s 35GBps. The new

Xeon 5600 series processor also supports low voltage (LV) 1.35V DIMMs.

Memory interleaving refers to how physical memory is interleaved across the physical DIMMs. A

balanced system provides the best interleaving. A Xeon 5600 processor-based system is balanced

when all memory channels on a socket have the same amount of memory.

A memory rank is simply a segment of memory that is addressed by a specific address bit. DIMMs

typically have 1, 2 or 4 memory ranks, as indicated by their size designation.

• A typical memory DIMM description is 2GB 4Rx8 DIMM

• The 4R designator is the rank count for this particular DIMM (4R = quad-rank)

• The x8 designator is the data width of the rank

It is important to ensure that DIMMs with appropriate number of ranks are populated in each channel

Ch1

Ch0

Ch2

Ch1

Ch0

Ch2

Xeon 5600 / 5500

Processor 0

Memory Controller

Xeon 5600 / 5500

Processor 1

QPI

Memory Controller

D10

D11

D12

D13

D14

D15

D16

1-16: DIMM population sequence; D1-D16: DIMM slot assignments

1 2 3 4 5 6 7 8 9 10 ... 18 19

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Lenovo x3400 M3 Betriebsanweisung Seite 5

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