Lenovo x3550 M3 Betriebsanweisung PDF herunterladen (Seite 6)

Leadership enterprise server with significantly lower cost of ownership in a highly available and

expandable, rack-dense, 1U dual-socket server

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DDR3 Memory with Chipkill ECC Protection

The x3550 M3 ships with registered double data rate III (DDR3) memory and provides Active

Memory features, including advanced Chipkill memory protection (using x4 DIMMs), for up to

16X better error correction than standard ECC memory. In addition to offering better performance

than DDR2 or fully-buffered memory, DDR3 memory also uses less energy. DDR2 memory

already offered up to 37% lower energy use than fully buffered memory. Now, a generation later,

DDR3 memory is even more efficient, using up to 15% less energy than DDR2 memory.

The x3550 M3 currently supports up to 144GB of RDIMM (registered DIMM) memory in 18 DIMM

slots (192GB in 12 slots), or up to 48GB of UDIMM (unbuffered DIMM) memory in 12 slots. The

x3550 M3 also supports either energy-efficient 1.35V DIMMs or standard 1.5V DIMMs. Redesign

in the architecture of the Xeon 5500 and 5600 series processors bring radical changes in the way

memory works in these servers. For example, the Xeon 5500 and 5600 series processors

integrate the memory controller inside the processor, resulting in two memory controllers in a

2-socket system. Each memory controller has three memory channels. Depending on the type of

memory, population of memory, and processor model, the memory may be clocked at 1333MHz,

1066MHz or 800MHz.

Note: If only one processor is installed, only the first nine DIMM slots can be used. Adding a

second processor not only doubles the amount of memory available for use, but also doubles the

number of memory controllers, thus doubling the system memory bandwidth. If you add a second

processor, but no additional memory for the second processor, the second processor would have

to access the memory from the first processor “remotely,” resulting in longer latencies and lower

performance. The latency to access remote memory is almost 75% higher than local memory

access. So, the goal should be to always populate both processors with memory.

The 1333MHz E56xx, L5640, and X56xx processor models support up to 1333MHz memory clock

speed and 2 DIMMs per channel (2DPC) at 1333MHz with single-rank and dual-rank RDIMMs and

UDIMMs running at 1.5V. Other processors access memory at 1066MHz.

Using 1333MHz memory (where supported) versus 1066MHz DIMMs offers up to 9% better

performance, while 1066MHz memory produces up to 28% better performance than 800MHz

memory. Xeon 5550/5600 series processors access memory with almost 50% lower latency than

the earlier 5400 series processors. That can result in faster processing of latency-sensitive

workloads.

Regardless of memory speed, the Xeon 5600 platform represents a significant improvement in

memory bandwidth over the previous Xeon 5400 platform. At 1333MHz, the improvement is

almost 500% over the previous generation. This huge improvement is mainly due to the dual

integrated memory controllers and faster DDR3 1333MHz memory. Throughput at 800MHz is 25

gigabytes per second (GBps); at 1066MHz it’s 32GBps; and at 1333MHz it’s 35GBps. This

improvement translates into improved application performance and scalability.

Memory interleaving refers to how physical memory is interleaved across the physical DIMMs. A

balanced system provides the best interleaving. A Xeon 5500/5600 processor-based system is

balanced when all memory channels on a socket have the same amount of memory.

The Xeon 5600 series processors support single-, dual-, and quad-rank memory. A memory rank

is simply a segment of memory that is addressed by a specific address bit.

A typical memory DIMM description is 8GB 2Rx4 DIMM:

1 2 3 4 5 6 7 8 9 10 11 ... 20 21

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