Lenovo LF80565QH0254M Datenblatt Seite 42
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Electrical Specifications
42 Document Number: 318080-002
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing
Voltage (V
CROSS
). PWRGOOD is referenced to BCLK0 rising edge at 0.5 * V
TT
.
3. These signals may be driven asynchronously.
4. Refer to Section 7.2 for additional timing requirements for entering and leaving low power states.
5. A minimum pulse width of 500 µs is recommended when FORCEPR# is asserted by the system
6. Refer to the PWRGOOD signal definition in Section 5 for more details information on behavior of the signal.
7. Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion
and before the deassertion of PROCHOT# for the processor to enable or disable the TCC.
8. Intel recommends the V
TT
power supply also be removed upon assertion of THERMTRIP#.
9. This specification requires that the VID and BSEL signals be sampled no earlier than 10 μs after V
CC
(at
V
CC_BOOT
voltage) and V
TT
are stable.
10. Parameter must be measured after applicable voltage level is stable. “Stable” means that the power supply
is in regulation as defined by the minimum and maximum DC/AC specifications for all components being
powered by it.
11. The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor.
Measured between (0.3* V
TT
) and (0.7*V
TT
).
12. See Table 2-19 for BCLK specifications.
Notes:
1. Before the clock that de-asserts RESET#
2. After the clock that de-asserts RESET#.
Table 2-22. Miscellaneous GTL+ AC Specifications
T# Parameter Min Max Unit Figure
Notes
1, 2, 3, 4
T35: Asynchronous GTL+ input pulse width 30 ns 5
T36: PWRGOOD assertion to RESET# de-assertion 1 10 ms 2-24
T37: BCLK stable to PWRGOOD assertion 10 BCLKs 2-24 6,12
T38: PROCHOT# pulse width 500 µs 2-20 7
T39: THERMTRIP# assertion until V
CC
removed 500 ms 2-21 8
T40: FERR# valid delay from STPCLK# deassertion 0 5 BCLKs 2-25
T41: V
CC
stable to PWRGOOD assertion 0.05 500 ms 2-24 10
T42: PWRGOOD rise time 20 ns 11
T43: V
CC_BOOT
stable to VID / BSEL valid 10 µs 2-24 9,10
T44: VID / BSEL valid to V
CC
stable 100 µs 2-24 10
T48: V
TT
stable to VID / BSEL valid 10 µs 2-24 10
T49: V
CCPLL
stable to PWRGOOD assertion 1 ms 2-24 10
Table 2-23. Front Side Bus AC Specifications (Reset Conditions)
T# Parameter Min Max Unit Figure Notes
T45: Reset Configuration Signals
(A[39:3]#, BR[1:0]#, INIT#, SMI#) Setup Time
480 µs 2-24 1
T46: Reset Configuration Signals
(A[39:3]#, INIT#, SMI#) Hold Time
220BCLKs2-24 2
T47: Reset Configuration Signals
BR[1:0]# Hold Time
22BCLKs2-24 2
Table 2-24. TAP Signal Group AC Specifications (Sheet 1 of 2)
T# Parameter Min Max Unit Figure
Notes
1, 2, 8
T55: TCK Period 30 ns 2-12 3
T56: TDI, TMS Setup Time 7.5 ns 2-19 4,7
- Processor 7200 Series 1
- Contents 3
- 4 Document Number: 318080-002 4
- Document Number: 318080-002 5 5
- 6 Document Number: 318080-002 6
- Document Number: 318080-002 7 7
- Revision History 8
- 1 Introduction 9
- 1.1 Terminology 11
- Introduction 12
- 1.2 State of Data 13
- 1.3 References 13
- 2 Electrical Specifications 15
- Clocking 16
- 2.3.2 PLL Power Supply 17
- Electrical Specifications 18
- Table 2-4. FSB Signal Groups 21
- Asynchronous Signals 22
- 2.9 Mixing Processors 23
- CC_VTT_OUT 27
- Time Duration (s) 28
- Sustained Current (A) 28
- Table 2-10. V 30
- Load Lines 32
- Static and Transient 34
- Tolerance Load Lines 34
- Specifications 35
- 2.11.2.1 DC Characteristics 36
- 2.11.3 V 37
- Overshoot Specification 37
- Example Overshoot Waveform 38
- Tp = T1: BCLK[1:0] period 47
- THERMTRIP# 51
- Figure 2-26. VID Step Timings 54
- 3 Mechanical Specifications 57
- Mechanical Specifications 58
- 3.7 Processor Materials 67
- 3.8 Processor Markings 68
- Processor 69
- 4 Pin Listing 71
- 10 of 16) 75
- 11 of 16) 76
- 12 of 16) 76
- 13 of 16) 77
- 14 of 16) 77
- 15 of 16) 78
- 16 of 16) 78
- 1 of 14) 79
- 2 of 14) 79
- 3 of 14) 80
- 4 of 14) 80
- 5 of 14) 81
- 6 of 14) 81
- 8 of 14) 82
- 7 of 14) 82
- 9 of 14) 83
- 10 of 14) 83
- 11 of 14) 84
- 12 of 14) 84
- 13 of 14) 85
- 14 of 14) 85
- Pin Listing 86
- 5 Signal Definitions 87
- CC and BCLK have reached 92
- 6 Thermal Specifications 95
- CASE_MAX 96
- Thermal Profile 98
- = 0.162 x Power + 45 98
- Pow er (W) 100
- Temperature (C) 100
- = 0.420 x Power + 45 100
- = 0.238 x Power + 45 101
- 6.1.2 Thermal Metrology 102
- 6.2.2 Thermal Monitor 103
- 6.2.3 Thermal Monitor 2 104
- 6.2.4 On-Demand Mode 105
- 6.2.5 PROCHOT# Signal 106
- 6.2.6 FORCEPR# Signal 106
- 6.2.7 THERMTRIP# Signal 106
- 6.3.1 Introduction 107
- 6.3.2 PECI Specifications 108
- 7 Features 111
- 7.2.1 Normal State 112
- EXTENDED_HALT 113
- 7.2.3 Stop-Grant State 114
- 7.3 Enhanced Intel SpeedStep 115
- Technology 115
- Features 116
- 7.4.1 SMBus Device Addressing 117
- Transactions 118
- 7.4.3.1 Header 121
- 7.4.3.2 Processor Data 125
- 7.4.3.3 Processor Core Data 126
- 16h-19h 127
- 1Ah-1Bh 127
- Offset: 1Ch 128
- 1Dh-1Eh 128
- 1Fh-20h 128
- 7.4.3.4 Cache Data 129
- 7.4.3.5 Package Data 131
- 7.4.3.6 Part Number Data 132
- 38h-3Eh 133
- 3Fh-4Ch 133
- 4Dh=54h 133
- 55h-6Eh 134
- 71h-72h 134
- 7.4.3.8 Feature Data 135
- 7.4.3.9 Other Data 136
- 7.4.4 Checksums 137
- 7.4.5 Scratch EEPROM 137
- 8.1 Introduction 139
- 8.2 Thermal Specifications 139
- 9 Debug Tools Specifications 141
- Debug Tools Specifications 142
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