Lenovo 59P5107 Datenblatt PDF herunterladen (Seite 81)

Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 81

BR0#

BR[1:3]#

I/O

BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The

BREQ[3:0]# signals are interconnected in a rotating manner to individual processor

pins. BR2# and BR3# must not be utilized in a dual processor platform design. The

table below gives the rotating interconnect between the processor and bus signals

for dual processor systems.

During power-on configuration, the central agent must assert the BR0# bus signal.

All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition

of RESET#. The pin which the agent samples asserted determines it’s agent ID.

These signals do not have on-die termination and must be terminated at the

end agent. See the appropriate platform design guidelines for additional

information.

BSEL[1:0]

These output signals are used to select the system bus frequency.

A BSEL[1:0] = 00 will select a 100 MHz bus clock frequency. The frequency is

determined by the processor(s), chipset, and frequency synthesizer capabilities. All

system bus agents must operate at the same frequency. Individual processors will

only operate at their specified front side bus (FSB) frequency.

On baseboards which support operation only at 100 MHz bus clocks these signals

may be ignored. On baseboards employing the use of these signals, a 1 K

Ω pull-up

resistor be used.

See Table 3, “System Bus Clock Frequency Select Truth Table for BSEL[1:0]” on

page 15 for output values.

COMP[1:0] I

COMP[1:0] must be terminated to V

on the baseboard using precision resistors.

These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate

platform design guidelines and Table 12 for implementation details.

Table 36. Signal Definitions (Sheet 3 of 9)

Name Type Description

BR[1:0]# Signals Rotating Interconnect, dual processor system

During power-up configuration, the central agent must assert the BR0# bus sign

al.

All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition o

RESET#. The pin on which the agent samples an active level determines its age

ID. All agents then configure their pins to match the appropriate bus signal proto

col

as shown below.

Bus Signal Agent 0 Pins Agent 1 Pins

BREQ0# BR0# BR1#

BREQ1# BR1# BR0#

BR[1:0]# Signal Agent IDs

BR[1:0]# Signals Rotating

Interconnect, dual processor system

Agent ID

BR0# 0

BR1# 1

1 2 ... 76 77 78 79 80 81 82 83 84 85 86 ... 101 102

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